diff options
| author | Jagannadha Sutradharudu Teki <jaganna@xilinx.com> | 2014-01-07 00:11:35 +0530 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jaganna@xilinx.com> | 2014-01-12 21:40:22 +0530 |
| commit | 056fbc73d54df64adcb93c513cba708acb2683bd (patch) | |
| tree | 4243a3f6eb6f1a2fabc57cdad08031fc4e351cd6 /doc/SPI/README.dual-flash | |
| parent | f77f469117ab3184ac45683a50dc446265be28cc (diff) | |
sf: Add dual memories support - DUAL_PARALLEL
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Diffstat (limited to 'doc/SPI/README.dual-flash')
| -rw-r--r-- | doc/SPI/README.dual-flash | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash index ba0aa265e0..6c88d65dd4 100644 --- a/doc/SPI/README.dual-flash +++ b/doc/SPI/README.dual-flash @@ -54,6 +54,33 @@ SF_DUAL_STACKED_FLASH: by default, if U_PAGE is unset lower memory should accessible, once user wants to access upper memory need to set U_PAGE. +SPI_FLASH_CONN_DUALPARALLEL: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating parallel with separate buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +-------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + | Controller | CS +---------------+ + | SPI/QSPI |---------------------->| | + | | I0[3:0] | Lower Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + +-------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. + - Operation: + Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory + and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. + Note: Technically there is only one CS line from the controller, but zynq qspi controller has an internal hw logic to enable additional CS when controller is configured for dual memories. |