diff options
| author | Michael Kurz <michi.kurz@gmail.com> | 2017-01-22 16:04:23 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-28 14:04:42 -0500 |
| commit | b1a8de7e07a6b40e7c5920566836862cd07df08a (patch) | |
| tree | 3071e082130d761e38d0c8811277d50891700050 /doc/device-tree-bindings/spi | |
| parent | 797c3c13a9b8fcedf134e30491496733becc3560 (diff) | |
ARM: DTS: stm32: add stm32f746-disco device tree files
This patch adds the DTS source files needed for stm32f746-disco board
The files are based on the stm32f429/469 files from current linux
kernel.
Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi"
Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Diffstat (limited to 'doc/device-tree-bindings/spi')
| -rw-r--r-- | doc/device-tree-bindings/spi/spi-stm32-qspi.txt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt new file mode 100644 index 0000000000..6c7da1d76c --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt @@ -0,0 +1,39 @@ +STM32 QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "st,stm32-qspi". +- reg : 1. Physical base address and size of SPI registers map. + 2. Physical base address & size of mapped NOR Flash. +- spi-max-frequency : Max supported spi frequency. +- status : enable in requried dts. + +Connected flash properties +-------------------------- +- spi-max-frequency : Max supported spi frequency. +- spi-tx-bus-width : Bus width (number of lines) for writing (1-4) +- spi-rx-bus-width : Bus width (number of lines) for reading (1-4) +- memory-map : Address and size for memory-mapping the flash + +Example: + qspi: quadspi@A0001000 { + compatible = "st,stm32-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <92>; + spi-max-frequency = <108000000>; + status = "okay"; + + qflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "spi-flash"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + memory-map = <0x90000000 0x1000000>; + reg = <0>; + }; + }; |