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authorTom Rini <trini@konsulko.com>2018-11-17 08:19:40 -0500
committerTom Rini <trini@konsulko.com>2018-11-17 08:19:40 -0500
commit0c4b382f9041f9f2f00246c8a0ece90dae5451be (patch)
treea2307a0658de178c47d7a063c169347e60e1810c /doc/device-tree-bindings
parent1d6edcbfed2af33c748f2beb399810a0441888da (diff)
parentad890cace37d0e2d3e0f9649bdb9c320947e4bb0 (diff)
Merge branch '2018-11-16-master-imports'
- Initial bcm968580xref, am65x_evm_r5 support - lpc32xx, omap3_logic/am3517_evm updates - pinctrl command - fs_loader available for SPL
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r--doc/device-tree-bindings/ram/k3-am654-ddrss.txt46
-rw-r--r--doc/device-tree-bindings/w1-eeprom/ds2502.txt33
2 files changed, 79 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt
new file mode 100644
index 0000000000..4ed731c524
--- /dev/null
+++ b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt
@@ -0,0 +1,46 @@
+Texas Instruments' K3 AM654 DDRSS
+=================================
+
+K3 based AM654 devices has DDR memory subsystem that comprises
+Synopys DDR controller, Synopsis DDR phy and wrapper logic to
+integrate these blocks into the device. This DDR subsystem
+provides an interface to external SDRAM devices. This DDRSS driver
+adds support for the initialization of the external SDRAM devices by
+configuring the DDRSS registers and using the buitin PHY
+initialization routines.
+
+DDRSS device node:
+==================
+Required properties:
+--------------------
+- compatible: Shall be: "ti,am654-ddrss"
+- reg-names ss - Map the sub system wrapper logic region
+ ctl - Map the controller region
+ phy - Map the PHY region
+- reg: Contains the register map per reg-names.
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DDRSS device id
+ value. This property is as per the binding,
+ doc/device-tree-bindings/power/ti,sci-pm-domain.txt
+- clocks: Must contain an entry for enabling DDR clock. Should
+ be defined as per the appropriate clock bindings consumer
+ usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
+
+
+Optional Properties:
+--------------------
+- clock-frequency: Frequency at which DDR pll should be locked.
+ If not provided, default frequency will be used.
+
+Example (AM65x):
+================
+ memory-controller: memory-controller@298e000 {
+ compatible = "ti,am654-ddrss";
+ reg = <0x0298e000 0x200>,
+ <0x02980000 0x4000>,
+ <0x02988000 0x2000>;
+ reg-names = "ss", "ctl", "phy";
+ clocks = <&k3_clks 20 0>;
+ power-domains = <&k3_pds 20>;
+ u-boot,dm-spl;
+ };
diff --git a/doc/device-tree-bindings/w1-eeprom/ds2502.txt b/doc/device-tree-bindings/w1-eeprom/ds2502.txt
new file mode 100644
index 0000000000..7f05fc432e
--- /dev/null
+++ b/doc/device-tree-bindings/w1-eeprom/ds2502.txt
@@ -0,0 +1,33 @@
+Maxim DS2502 driver device binding - one wire protocol add only memory from Maxim
+=======================
+
+This memory needs to be connected to a onewire bus, as a child node.
+The bus will read the device serial number and match this node with a found
+device on the bus
+Also check doc/device-tree-bindings/w1 for onewire bus drivers
+
+Driver:
+- drivers/w1-eeprom/ds2502.c
+
+Ds2502 device-tree node properties:
+Required:
+* compatible = "maxim,ds2502"
+
+Optional:
+* none
+
+Example:
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds2502";
+ };
+
+Example with parent bus:
+ onewire {
+ compatible = "fsl,imx53-owire";
+ reg = <0x63fa4000 0x4000>;
+
+ eeprom1: eeprom@0 {
+ compatible = "maxim,ds2502";
+ };
+ };
+