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| author | Tom Rini <trini@konsulko.com> | 2016-05-23 18:32:47 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-05-23 18:32:47 -0400 |
| commit | 6d54868eeb2697c9a905c4d3521efbacc44c5258 (patch) | |
| tree | 6ad3ae03a0083d1a50a6152bd6dcad5630ce7823 /doc/device-tree-bindings | |
| parent | d7d000311285e4b8d11e089ca13ea456a01be3b8 (diff) | |
| parent | 8216b11cdd50515fbc423a4b2709a00865b8621d (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-x86
Diffstat (limited to 'doc/device-tree-bindings')
| -rw-r--r-- | doc/device-tree-bindings/misc/intel,irq-router.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt index e4d8ead2ee..04ad34654c 100644 --- a/doc/device-tree-bindings/misc/intel,irq-router.txt +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -14,6 +14,11 @@ Required properties : "ibase": IRQ routing is in the memory-mapped IBASE register block - intel,ibase-offset : IBASE register offset in the interrupt router's PCI configuration space, required only if intel,pirq-config = "ibase". +- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must + be specified. The 8-bit ACTL register is seen on ICH series chipset, like + ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. +- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either + in the interrupt router's PCI configuration space, or IBASE. - intel,pirq-link : Specifies the PIRQ link information with two cells. The first cell is the register offset that controls the first PIRQ link routing. The second cell is the total number of PIRQ links the router supports. |