diff options
author | Sean Anderson <seanga2@gmail.com> | 2020-06-24 06:41:11 -0400 |
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committer | Andes <uboot@andestech.com> | 2020-07-01 15:01:21 +0800 |
commit | f9c7d4f99f51ac9c1cf513111c21395f93d2dd53 (patch) | |
tree | ba01f5f1a843d36582654975fd4ad3413e4f6e40 /doc/device-tree-bindings | |
parent | 1a198cf8862b0540894ba6569c55244b1bd3e824 (diff) |
clk: Add K210 clock support
Due to the large number of clocks, I decided to use the CCF. The overall
structure is modeled after the imx code. Clocks parameters are stored in
several arrays, and are then instantiated at run-time. There are some
translation macros (FOOIFY()) which allow for more dense packing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
CC: Lukasz Majewski <lukma@denx.de>
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r-- | doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt new file mode 100644 index 0000000000..5b24abcb62 --- /dev/null +++ b/doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt @@ -0,0 +1,33 @@ +Kendryte K210 Sysctl + +This binding describes the K210 sysctl device, which contains many miscellaneous +registers controlling system functionality. This node is a register map and can +be reference by other bindings which need a phandle to the K210 sysctl regmap. + +Required properties: +- compatible: should be + "kendryte,k210-sysctl", "syscon", "simple-mfd" +- reg: address and length of the sysctl registers +- reg-io-width: must be <4> + +Clock sub-node + +This node is a binding for the clock tree driver + +Required properties: +- compatible: should be "kendryte,k210-clk" +- clocks: phandle to the "in0" external oscillator +- #clock-cells: must be <1> + +Example: +sysctl: syscon@50440000 { + compatible = "kendryte,k210-sysctl", "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + reg-io-width = <4>; + + sysclk: clock-controller { + compatible = "kendryte,k210-clk"; + clocks = <&in0>; + #clock-cells = <1>; + }; +}; |