diff options
author | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
commit | c1b62ba9ca0e41fdd548cb3bb9af3b3f90d4a393 (patch) | |
tree | 7e653a1823011bfb075540428bfdab96707f1517 /doc | |
parent | bc5d0384458466ed5b3608d326eec03cd4f13016 (diff) | |
parent | 217273cd441fe3d00a1bdad143dcb656854963f9 (diff) |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'doc')
-rw-r--r-- | doc/README.rockchip | 2 | ||||
-rw-r--r-- | doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt | 67 |
2 files changed, 68 insertions, 1 deletions
diff --git a/doc/README.rockchip b/doc/README.rockchip index dbeb8be6c0..12fec38139 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -130,7 +130,7 @@ load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom. Therefore RK3288 has another loading sequence like RK3036. The option of U-Boot is controlled with this setting in U-Boot: - #define CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + #define CONFIG_SPL_ROCKCHIP_BACK_TO_BROM You can create the image via the following operations: diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt new file mode 100644 index 0000000000..8e7357d53d --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt @@ -0,0 +1,67 @@ +RK3368 dynamic memory controller driver +======================================= + +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on +the following key configuration data: + (a) a target-frequency (i.e. operating point) for the memory operation + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware + (c) a memory-schedule (i.e. mapping from physical addresses to the address + pins of the memory bus) + +Required properties +------------------- + +- compatible: "rockchip,rk3368-dmc" +- reg + protocol controller (PCTL) address and PHY controller (DDRPHY) address +- rockchip,ddr-speed-bin + the DDR3 device's speed-bin (as specified according to JESD-79) + DDR3_800D (5-5-5) + DDR3_800E (6-6-6) + DDR3_1066E (6-6-6) + DDR3_1066F (7-7-7) + DDR3_1066G (8-8-8) + DDR3_1333F (7-7-7) + DDR3_1333G (8-8-8) + DDR3_1333H (9-9-9) + DDR3_1333J (10-10-10) + DDR3_1600G (8-8-8) + DDR3_1600H (9-9-9) + DDR3_1600J (10-10-10) + DDR3_1600K (11-11-11) + DDR3_1866J (10-10-10) + DDR3_1866K (11-11-11) + DDR3_1866L (12-12-12) + DDR3_1866M (13-13-13) + DDR3_2133K (11-11-11) + DDR3_2133L (12-12-12) + DDR3_2133M (13-13-13) + DDR3_2133N (14-14-14) +- rockchip,ddr-frequency: + target DDR clock frequency in Hz (not all frequencies may be supported, + as there's some cooperation from the clock-driver required) +- rockchip,memory-schedule: + controls the decoding of physical addresses to DRAM addressing (i.e. how + the physical address maps onto the address pins/chip-select of the device) + DMC_MSCH_CBDR: column -> bank -> device -> row + DMC_MSCH_CBRD: column -> band -> row -> device + DMC_MSCH_CRBD: column -> row -> band -> device + +Example (for DDR3-1600K and 800MHz) +----------------------------------- + + #include <dt-bindings/memory/rk3368-dmc.h> + + dmc: dmc@ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc"; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + &dmc { + rockchip,ddr-speed-bin = <DDR3_1600K>; + rockchip,ddr-frequency = <800000000>; + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + }; |