Merge /home/roy/CVS/7448/Open_Source/u-boot.git.dev

2 files changed, 225 insertions, 107 deletions

diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2
index 5142a0f638..0e40e39269 100644
--- a/doc/README.mpc7448hpc2
+++ b/doc/README.mpc7448hpc2
@@ -3,23 +3,23 @@ Freescale MPC7448hpc2 (Taiga) board
 
 Created 08/11/2006 Roy Zang
 --------------------------
-MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference 
-design, which is optimized for high speed throughput between the processor and 
+MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
+design, which is optimized for high speed throughput between the processor and
 the memory, disk drive and Ethernet port subsystems.
 
-MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be 
-used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX 
+MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
+used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
 chassis.
 
 Building U-Boot
 ------------------
 The mpc7448hpc2 code base is known to compile using:
-    Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+	Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
 
-    $ make mpc7448hpc2_config
-    Configuring for mpc7448hpc2 board...
+	$ make mpc7448hpc2_config
+	Configuring for mpc7448hpc2 board...
 
-    $ make
+	$ make
 
 Memory Map
 ----------
@@ -28,25 +28,24 @@ The memory map is setup for Linux to operate properly.
 
 The mapping is:
 
-   Range Start     Range End       Definition              	Size
-
-   0x0000_0000     0x7fff_ffff     DDR                     	2G
-   0xe000_0000     0xe7ff_ffff     PCI Memory              	128M
-   0xfa00_0000     0xfaff_ffff     PCI IO                  	16M
-   0xfb00_0000     0xfbff_ffff     PCI Config              	16M
-   0xfc00_0000     0xfc0f_ffff     NVRAM/CADMUS            	1M
-   0xfe00_0000	   0xfeff_ffff	   PromJet		   	16M
-   0xff00_0000     0xff80_0000     FLASH (boot flash)      	8M
-   0xff80_0000     0xffff_ffff     FLASH (second half flash)	8M
+	Range Start	Range End	Definition			Size
 
+	0x0000_0000	0x7fff_ffff	DDR				2G
+	0xe000_0000	0xe7ff_ffff	PCI Memory			128M
+	0xfa00_0000	0xfaff_ffff	PCI IO				16M
+	0xfb00_0000	0xfbff_ffff	PCI Config			16M
+	0xfc00_0000	0xfc0f_ffff	NVRAM/CADMUS			1M
+	0xfe00_0000	0xfeff_ffff	PromJet				16M
+	0xff00_0000	0xff80_0000	FLASH (boot flash)		8M
+	0xff80_0000	0xffff_ffff	FLASH (second half flash)	8M
 
 Using Flash
 -----------
 
-The MPC7448hpc2 board has two "banks" of flash, each 8MB in size 
-(2^23 = 0x00800000). 
+The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
+(2^23 = 0x00800000).
 
-Note: the "bank" here refers to half of the flash. In fact, there is only one 
+Note: the "bank" here refers to half of the flash. In fact, there is only one
 bank of flash, which is divided into low and high half. Each is controlled by
 the most significant bit of the address bus. The so called "bank" is only for
 convenience.
@@ -57,137 +56,130 @@ settings for updating flash are given below.
 The u-boot commands for copying the boot-bank into the secondary bank are
 as follows:
 
-     erase ff800000 ff880000
-     cp.b ff000000 ff800000 80000
+	erase ff800000 ff880000
+	cp.b ff000000 ff800000 80000
 
 U-boot commands for downloading an image via tftp and flashing
 it into the secondary bank:
 
-     tftp 10000 <u-boot.bin.image>
-     erase ff000000 ff080000
-     cp.b 10000 ff000000 80000
-
+	tftp 10000 <u-boot.bin.image>
+	erase ff000000 ff080000
+	cp.b 10000 ff000000 80000
 
 After copying the image into the second bank of flash, be sure to toggle
 SW3[4] on board before resetting the board in order to set the
 secondary bank as the boot-bank.
 
-
 Board Switches
 ----------------------
 
-
 Most switches on the board should not be changed.  The most frequent
 user-settable switches on the board are used to configure
 the flash banks and determining the PCI frequency.
 
 SW1[1-5]: Processor core voltage
 
-      12345		Core Voltage
-      -----
-  SW1=01111	   	   1.000V.
-  SW1=01101	   	   1.100V.
-  SW1=01011	   	   1.200V.
-  SW1=01001	   	   1.300V only for MPC7447A.
+	12345		Core Voltage
+	-----
+	SW1=01111	1.000V.
+	SW1=01101	1.100V.
+	SW1=01011	1.200V.
+	SW1=01001	1.300V only for MPC7447A.
 
 
 SW2[1-6]: CPU core frequency
 
-		  CPU Core Frequency (MHz)
+		CPU Core Frequency (MHz)
 			Bus Frequency
-      123456	100	133	167	200	 Ratio
+	123456		100	133	167	200	Ratio
 	
-      ------
-  SW2=101100	500	667	833	1000	   5x
-  SW2=100100	550	733	917	1100	   5.5x
-  SW2=110100	600	800	1000	1200	   6x
-  SW2=010100	650	866	1083	1300	   6.5x
-  SW2=001000	700	930	1167	1400	   7x
-  SW2=000100	750	1000	1250	1500	   7.5x
-  SW2=110000	800	1066	1333	1600	   8x
-  SW2=011000	850	1333	1417	1700	   8.5x only for MPC7447A
-  SW2=011110	900	1200	1500	1800	   9x
-
-This table shows only a subset of available frequency options; see the CPU 
+	------
+	SW2=101100	500	667	833	1000	5x
+	SW2=100100	550	733	917	1100	5.5x
+	SW2=110100	600	800	1000	1200	6x
+	SW2=010100	650	866	1083	1300	6.5x
+	SW2=001000	700	930	1167	1400	7x
+	SW2=000100	750	1000	1250	1500	7.5x
+	SW2=110000	800	1066	1333	1600	8x
+	SW2=011000	850	1333	1417	1700	8.5x only for MPC7447A
+	SW2=011110	900	1200	1500	1800	9x
+
+This table shows only a subset of available frequency options; see the CPU
 hardware specifications for more information.
 
-
 SW2[7-8]: Bus Protocol and CPU Reset Option
 
-      7		
-      -
-  SW2=0	   	System bus uses MPX bus protocol
-  SW2=1		System bus uses 60x bus protocol
-
-      8		
-      -
-  SW2=0	   	TSI108 can cause CPU reset
-  SW2=1		TSI108 can not cause CPU reset
+	7		
+	-
+	SW2=0		System bus uses MPX bus protocol
+	SW2=1		System bus uses 60x bus protocol
 
+	8		
+	-
+	SW2=0		TSI108 can cause CPU reset
+	SW2=1		TSI108 can not cause CPU reset
 
 SW3[1-8] system options
 
-      123		
-      ---
-  SW3=xxx	   	Connected to GPIO[0:2] on TSI108
+	123		
+	---
+	SW3=xxx		Connected to GPIO[0:2] on TSI108
 
-      4		
-      -
-  SW3=0	   	CPU boots from low half of flash
-  SW3=1		CPU boots from high half of flash
+	4		
+	-
+	SW3=0		CPU boots from low half of flash
+	SW3=1		CPU boots from high half of flash
 
-      5		
-      -
-  SW3=0	   	SATA and slot2 connected to PCI bus
-  SW3=1		Only slot1 connected to PCI bus
+	5		
+	-
+	SW3=0		SATA and slot2 connected to PCI bus
+	SW3=1		Only slot1 connected to PCI bus
 
-      6		
-      -
-  SW3=0	   	USB connected to PCI bus
-  SW3=1		USB disconnected from PCI bus
+	6		
+	-
+	SW3=0		USB connected to PCI bus
+	SW3=1		USB disconnected from PCI bus
 
-      7		
-      -
-  SW3=0	   	Flash is write protected
-  SW3=1		Flash is NOT write protected
+	7		
+	-
+	SW3=0		Flash is write protected
+	SW3=1		Flash is NOT write protected
 
-      8		
-      -
-  SW3=0	   	CPU will boot from flash
-  SW3=1		CPU will boot from PromJet
+	8		
+	-
+	SW3=0		CPU will boot from flash
+	SW3=1		CPU will boot from PromJet
 
 SW4[1-3]: System bus frequency
 
 			Bus Frequency (MHz)
-      ---
-  SW4=010			183
-  SW4=011			100
-  SW4=100			133
-  SW4=101			166 only for MPC7447A
-  SW4=110			200 only for MPC7448
-  others			reserved
-	
+	---
+	SW4=010			183
+	SW4=011			100
+	SW4=100			133
+	SW4=101			166 only for MPC7447A
+	SW4=110			200 only for MPC7448
+	others			reserved
 
 SW4[4-6]: DDR2 SDRAM frequency
 
 			Bus Frequency (MHz)
-      ---
-  SW4=000		   external clock
-  SW4=011		   system clock	
-  SW4=100			133
-  SW4=101			166
-  SW4=110			200
-  others			reserved
-
+	---
+	SW4=000		external clock
+	SW4=011		system clock	
+	SW4=100		133
+	SW4=101		166
+	SW4=110		200
+	others		reserved
 
 SW4[7-8]: PCI/PCI-X frequency control
-      7		
-      -
-  SW4=0	   	PCI/PCI-X bus operates normally
-  SW4=1		PCI bus forced to PCI-33 mode
-
-      8		
-      -
-  SW4=0	   	PCI-X mode at 133 MHz allowed
-  SW4=1		PCI-X mode limited to 100 MHz
+	7		
+	-
+	SW4=0		PCI/PCI-X bus operates normally
+	SW4=1		PCI bus forced to PCI-33 mode
+
+	8		
+	-
+	SW4=0		PCI-X mode at 133 MHz allowed
+	SW4=1		PCI-X mode limited to 100 MHz
 
diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds
new file mode 100644
index 0000000000..c87469f43d
--- /dev/null
+++ b/doc/README.mpc8360emds
@@ -0,0 +1,126 @@
+Freescale MPC8360EMDS Board
+-----------------------------------------
+1.	Board Switches and Jumpers
+1.0 	There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
+	For some reason, the HW designers describe the switch settings
+	in terms of 0 and 1, and then map that to physical switches where
+	the label "On" refers to logic 0 and "Off" is logic 1.
+
+	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+	bits may contribute to signals that are numbered based at 0,
+	and some of those signals may be high-bit-number-0 too.  Heed
+	well the names and labels and do not get confused.
+
+		"Off" == 1
+		"On"  == 0
+
+	SW18 is switch 18 as silk-screened onto the board.
+	SW4[8] is the bit labled 8 on Switch 4.
+	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+	SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
+	SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+		and bits labeled 8 is set as "Off".
+
+1.1	For the MPC8360E PB PROTO Board
+
+	First, make sure the board default setting is consistent with the
+	document shipped with your board. Then apply the following setting:
+	SW3[1-8]= 0000_0100  (HRCW setting value is performed on local bus)
+	SW4[1-8]= 0011_0000  (Flash boot on local bus)
+	SW9[1-8]= 0110_0110  (PCI Mode enabled. HRCW is read from FLASH)
+	SW10[1-8]= 0000_1000  (core PLL setting)
+	SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
+	JP6 1-2
+	on board Oscillator: 66M
+
+
+2.	Memory Map
+
+2.1.	The memory map should look pretty much like this:
+
+	0x0000_0000	0x7fff_ffff	DDR			2G
+	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
+	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
+	0xc000_0000	0xdfff_ffff	Empty			512M
+	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
+	0xe020_0000	0xe02f_ffff	Empty			1M
+	0xe030_0000	0xe03f_ffff	PCI IO			1M
+	0xe040_0000	0xefff_ffff	Empty			252M
+	0xf000_0000	0xf3ff_ffff	Local Bus SDRAM		64M
+	0xf400_0000	0xf7ff_ffff	Empty			64M
+	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
+	0xf800_8000	0xf800_ffff	PIB CS4			32K
+	0xf801_0000	0xf801_7fff	PIB CS5			32K
+	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC8360EMDS.h
+
+    CONFIG_MPC83XX	    MPC83xx family for both MPC8349 and MPC8360
+    CONFIG_MPC8360	    MPC8360 specific
+    CONFIG_MPC8360EMDS	    MPC8360EMDS board specific
+
+4. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make MPC8360EMDS_config
+		make
+
+	MPC8360 support PCI in host and slave mode.
+
+	To make u-boot support PCI host 66M :
+	1) DIP SW support PCI mode as described in Section 1.1.
+	2) Make MPC8360EMDS_HOST_66_config
+
+	To make u-boot support PCI host 33M :
+	1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
+	2) Make MPC8360EMDS_HOST_33_config
+
+	To make u-boot support PCI slave 66M :
+	1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
+	2) Make MPC8360EMDS_SLAVE_config
+
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+	loadb
+	[Drop to kermit:
+	    ^\c
+	    send <u-boot-bin-image>
+	    c
+	]
+
+
+    Or via tftp:
+
+	tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+	tftp 20000 u-boot.bin
+	protect off fef00000 fef3ffff
+	erase fef00000 fef3ffff
+
+	cp.b 20000 fef00000 xxxx
+
+	or
+
+	cp.b 20000 fef00000 3ffff
+
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+	1) The console baudrate for MPC8360EMDS is 115200bps.