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author | Reinhard Pfau <reinhard.pfau@gdsys.cc> | 2016-03-16 09:20:13 +0100 |
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committer | Stefan Roese <sr@denx.de> | 2016-03-21 09:20:37 +0100 |
commit | a119357c43a4d4bd0e488a701255bcfea8f8bf6c (patch) | |
tree | 158ed8e068ebbfa6b283937fe6c98b3c41a56d9b /drivers/block/fsl_sata.h | |
parent | 4709805657db221b05192d575392ebfd977ee1d2 (diff) |
strider: use optimised bus timing for FPGA access
Use optimised bus timing for FPGA access.
Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Diffstat (limited to 'drivers/block/fsl_sata.h')
0 files changed, 0 insertions, 0 deletions