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authorTom Rini <trini@konsulko.com>2019-09-02 23:21:44 -0400
committerTom Rini <trini@konsulko.com>2019-09-02 23:21:44 -0400
commit83a5df42614c566c3c642871f683e66a53d228ae (patch)
treeea53c8fd1dd9bf65bc1d29dd9a0957d060dc1917 /drivers/cache/cache-uclass.c
parentd22c8be964a870f59d2fdab6c67cefa0c4799364 (diff)
parent61ce84b2cf1a6672c8e402ce8174554b25629692 (diff)
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Skip unavailable hart in the get_count(). - fu540 set serial env from otp. - fu540 add mmc0 as a boot target device. - Update fix_rela_dyn and add absolute reloc addend. - Andestech PLIC driver will skip unavailable hart. - Support Andestech V5L2 cache driver.
Diffstat (limited to 'drivers/cache/cache-uclass.c')
-rw-r--r--drivers/cache/cache-uclass.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce0249a4..3b20a10f08 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info *info)
return ops->get_info(dev, info);
}
+int cache_enable(struct udevice *dev)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->enable)
+ return -ENOSYS;
+
+ return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+ struct cache_ops *ops = cache_get_ops(dev);
+
+ if (!ops->disable)
+ return -ENOSYS;
+
+ return ops->disable(dev);
+}
+
UCLASS_DRIVER(cache) = {
.id = UCLASS_CACHE,
.name = "cache",