diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2019-10-04 15:52:43 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-10-24 13:37:01 +0200 |
| commit | 6596270ecb5d74d5f997da0daa728e06d1f47029 (patch) | |
| tree | 21d5b8265b2fa0e02297c0ee8edae46b9362a3cc /drivers/clk/clk_versal.c | |
| parent | 866225f394a9b3174d9ea39d2d19ac0d2c07a516 (diff) | |
arm64: versal: Rename versal_pm_request to xilinx_pm_request
Use generic name instead of Versal specific because this should be also
used on ZynqMP.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/clk/clk_versal.c')
| -rw-r--r-- | drivers/clk/clk_versal.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index e0fa661be9..7e97b0c4bf 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -363,7 +363,7 @@ static u32 versal_clock_get_div(u32 clk_id) u32 ret_payload[PAYLOAD_ARG_CNT]; u32 div; - versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); div = ret_payload[1]; return div; @@ -373,7 +373,7 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div) { u32 ret_payload[PAYLOAD_ARG_CNT]; - versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); return div; } @@ -383,7 +383,7 @@ static u64 versal_clock_ref(u32 clk_id) u32 ret_payload[PAYLOAD_ARG_CNT]; int ref; - versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); ref = ret_payload[0]; if (!(ref & 1)) return ref_clk; @@ -402,7 +402,7 @@ static u64 versal_clock_get_pll_rate(u32 clk_id) u32 parent_rate, parent_id; u32 id = clk_id & 0xFFF; - versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); res = ret_payload[1]; if (!res) { printf("0%x PLL not enabled\n", clk_id); @@ -412,9 +412,9 @@ static u64 versal_clock_get_pll_rate(u32 clk_id) parent_id = clock[clock[id].parent[0].id].clk_id; parent_rate = versal_clock_ref(parent_id); - versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); fbdiv = ret_payload[1]; - versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); frac = ret_payload[1]; freq = (fbdiv * parent_rate) >> (1 << frac); @@ -441,7 +441,7 @@ static u32 versal_clock_get_parentid(u32 clk_id) u32 id = clk_id & 0xFFF; if (versal_clock_mux(clk_id)) { - versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, + xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); parent_id = ret_payload[1]; } |