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authorPeng Fan <peng.fan@nxp.com>2019-10-22 03:29:48 +0000
committerStefano Babic <sbabic@denx.de>2019-11-05 10:27:18 +0100
commit3bdd5587378cb7b456476e73d17c74a1852e0a8f (patch)
tree4015934fe389817b940483086ef03cc59251bc3a /drivers/clk/imx
parentcd7c806f4f58fe66895f4355b1ddd88460925a01 (diff)
clk: imx8mm: add enet clk
Add enet ref/timer/PHY_REF/root clk which are required to make enet function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r--drivers/clk/imx/clk-imx8mm.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index f4913e70ab..4911345fd9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -80,6 +80,17 @@ static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_80
static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
"sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+#ifndef CONFIG_SPL_BUILD
+static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
+ "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "video_pll1_out", };
+
+static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
+ "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+#endif
+
static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
@@ -363,6 +374,22 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_CLK_USDHC3_ROOT,
imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+ /* clks not needed in SPL stage */
+#ifndef CONFIG_SPL_BUILD
+ clk_dm(IMX8MM_CLK_ENET_REF,
+ imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
+ base + 0xa980));
+ clk_dm(IMX8MM_CLK_ENET_TIMER,
+ imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
+ base + 0xaa00));
+ clk_dm(IMX8MM_CLK_ENET_PHY_REF,
+ imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
+ base + 0xaa80));
+ clk_dm(IMX8MM_CLK_ENET1_ROOT,
+ imx_clk_gate4("enet1_root_clk", "enet_axi",
+ base + 0x40a0, 0));
+#endif
+
#ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;