diff options
| author | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
| commit | c1b62ba9ca0e41fdd548cb3bb9af3b3f90d4a393 (patch) | |
| tree | 7e653a1823011bfb075540428bfdab96707f1517 /drivers/clk/rockchip/clk_rk3036.c | |
| parent | bc5d0384458466ed5b3608d326eec03cd4f13016 (diff) | |
| parent | 217273cd441fe3d00a1bdad143dcb656854963f9 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3036.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3036.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 5ecf5129d8..83f4ae6ca3 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -235,7 +235,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, } src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; - return DIV_TO_RATE(src_rate, div); + return DIV_TO_RATE(src_rate, div) / 2; } static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, @@ -247,10 +247,11 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); /* mmc clock auto divide 2 in internal */ - src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); - if (src_clk_div > 0x7f) { - src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + if (src_clk_div > 128) { + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); + assert(src_clk_div - 1 < 128); mux = EMMC_SEL_24M; } else { mux = EMMC_SEL_GPLL; |