Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

4 files changed, 557 insertions, 52 deletions

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 1091a76f05..e404c0cdb9 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -8,4 +8,6 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
+obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 0bee5db69b..28652df72d 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -65,12 +65,11 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
 	rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
 
 	rk_clrsetreg(&pll->con0,
-		     PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
 		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
-	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
-			PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
-			(div->postdiv2 << PLL_POSTDIV2_SHIFT |
-			 div->refdiv << PLL_REFDIV_SHIFT));
+	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
+		     div->refdiv << PLL_REFDIV_SHIFT));
 
 	/* waiting for pll lock */
 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
@@ -87,8 +86,7 @@ static void rkclk_init(struct rk3036_cru *cru)
 
 	/* pll enter slow-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
-		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
-		     APLL_MODE_MASK << APLL_MODE_SHIFT,
+		     GPLL_MODE_MASK | APLL_MODE_MASK,
 		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
 
@@ -97,8 +95,8 @@ static void rkclk_init(struct rk3036_cru *cru)
 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 
 	/*
-	 * select apll as core clock pll source and
-	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 * select apll as cpu/core clock pll source and
+	 * set up dependent divisors for PERI and ACLK clocks.
 	 * core hz : apll = 1:1
 	 */
 	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
@@ -108,44 +106,40 @@ static void rkclk_init(struct rk3036_cru *cru)
 	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
 
 	rk_clrsetreg(&cru->cru_clksel_con[0],
-		     CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT |
-		     CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT,
+		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
 		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
 		     0 << CORE_DIV_CON_SHIFT);
 
 	rk_clrsetreg(&cru->cru_clksel_con[1],
-		     CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT |
-		     CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
+		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
 		     aclk_div << CORE_ACLK_DIV_SHIFT |
 		     pclk_div << CORE_PERI_DIV_SHIFT);
 
 	/*
-	 * select apll as cpu clock pll source and
+	 * select apll as pd_bus bus clock source and
 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 	 */
-	aclk_div = APLL_HZ / CPU_ACLK_HZ - 1;
-	assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f);
+	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
+	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
-	pclk_div = APLL_HZ / CPU_PCLK_HZ - 1;
-	assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7);
+	pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
+	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
 
-	hclk_div = APLL_HZ / CPU_HCLK_HZ - 1;
-	assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3);
+	hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
+	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
 
 	rk_clrsetreg(&cru->cru_clksel_con[0],
-		     CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT |
-		     ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT,
-		     CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT |
-		     aclk_div << ACLK_CPU_DIV_SHIFT);
+		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
+		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
+		     aclk_div << BUS_ACLK_DIV_SHIFT);
 
 	rk_clrsetreg(&cru->cru_clksel_con[1],
-		     CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
-		     CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
-		     pclk_div << CPU_PCLK_DIV_SHIFT |
-		     hclk_div << CPU_HCLK_DIV_SHIFT);
+		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
+		     pclk_div << BUS_PCLK_DIV_SHIFT |
+		     hclk_div << BUS_HCLK_DIV_SHIFT);
 
 	/*
-	 * select gpll as peri clock pll source and
+	 * select gpll as pd_peri bus clock source and
 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 	 */
 	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
@@ -153,17 +147,15 @@ static void rkclk_init(struct rk3036_cru *cru)
 
 	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 	assert((1 << hclk_div) * PERI_HCLK_HZ ==
-		PERI_ACLK_HZ && (pclk_div < 0x4));
+		PERI_ACLK_HZ && (hclk_div < 0x4));
 
 	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 	assert((1 << pclk_div) * PERI_PCLK_HZ ==
 		PERI_ACLK_HZ && pclk_div < 0x8);
 
 	rk_clrsetreg(&cru->cru_clksel_con[10],
-		     PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT |
-		     PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
-		     PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
-		     PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
+		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
+		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
 		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
 		     pclk_div << PERI_PCLK_DIV_SHIFT |
 		     hclk_div << PERI_HCLK_DIV_SHIFT |
@@ -171,8 +163,7 @@ static void rkclk_init(struct rk3036_cru *cru)
 
 	/* PLL enter normal-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
-		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
-		     APLL_MODE_MASK << APLL_MODE_SHIFT,
+		     GPLL_MODE_MASK | APLL_MODE_MASK,
 		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
 		     APLL_MODE_NORM << APLL_MODE_SHIFT);
 }
@@ -189,9 +180,9 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
 		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
 		GPLL_MODE_SHIFT, 0xff
 	};
-	static u8 clk_mask[CLK_COUNT] = {
-		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
-		GPLL_MODE_MASK, 0xff
+	static u32 clk_mask[CLK_COUNT] = {
+		0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
+		GPLL_MODE_MASK, 0xffffffff
 	};
 	uint shift;
 	uint mask;
@@ -200,18 +191,18 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
 	shift = clk_shift[clk_id];
 	mask = clk_mask[clk_id];
 
-	switch ((con >> shift) & mask) {
+	switch ((con & mask) >> shift) {
 	case GPLL_MODE_SLOW:
 		return OSC_HZ;
 	case GPLL_MODE_NORM:
 
 		/* normal mode */
 		con = readl(&pll->con0);
-		postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK;
-		fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK;
+		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
+		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
 		con = readl(&pll->con1);
-		postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK;
-		refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK;
+		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
+		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
 		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
 	case GPLL_MODE_DEEP:
 	default:
@@ -230,14 +221,14 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
 	case HCLK_EMMC:
 	case SCLK_EMMC:
 		con = readl(&cru->cru_clksel_con[12]);
-		mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
-		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
+		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
+		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 		break;
 	case HCLK_SDIO:
 	case SCLK_SDIO:
 		con = readl(&cru->cru_clksel_con[12]);
-		mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
-		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
+		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
+		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 		break;
 	default:
 		return -EINVAL;
@@ -269,16 +260,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
 	case HCLK_EMMC:
 	case SCLK_EMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
-			     EMMC_PLL_MASK << EMMC_PLL_SHIFT |
-			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
+			     EMMC_PLL_MASK | EMMC_DIV_MASK,
 			     mux << EMMC_PLL_SHIFT |
 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
 		break;
 	case HCLK_SDIO:
 	case SCLK_SDIO:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
-			     MMC0_PLL_MASK << MMC0_PLL_SHIFT |
-			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
+			     MMC0_PLL_MASK | MMC0_DIV_MASK,
 			     mux << MMC0_PLL_SHIFT |
 			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
 		break;
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
new file mode 100644
index 0000000000..52cad38446
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3368-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pll_div {
+	u32 nr;
+	u32 nf;
+	u32 no;
+};
+
+#define OSC_HZ		(24 * 1000 * 1000)
+#define APLL_L_HZ	(800 * 1000 * 1000)
+#define APLL_B_HZ	(816 * 1000 * 1000)
+#define GPLL_HZ		(576 * 1000 * 1000)
+#define CPLL_HZ		(400 * 1000 * 1000)
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+		((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _nr, _no) { \
+	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
+	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
+		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
+		       "divisors on line " __stringify(__LINE__));
+
+static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
+static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
+				   enum rk3368_pll_id pll_id)
+{
+	uint32_t nr, no, nf;
+	uint32_t con;
+	struct rk3368_pll *pll = &cru->pll[pll_id];
+
+	con = readl(&pll->con3);
+
+	switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
+	case PLL_MODE_SLOW:
+		return OSC_HZ;
+	case PLL_MODE_NORMAL:
+		con = readl(&pll->con0);
+		no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
+		nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
+		con = readl(&pll->con1);
+		nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
+
+		return (24 * nf / (nr * no)) * 1000000;
+	case PLL_MODE_DEEP_SLOW:
+	default:
+		return 32768;
+	}
+}
+
+static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
+			 const struct pll_div *div, bool has_bwadj)
+{
+	struct rk3368_pll *pll = &cru->pll[pll_id];
+	/* All PLLs have same VCO and output frequency range restrictions*/
+	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
+	uint output_hz = vco_hz / div->no;
+
+	debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
+	      pll, div->nf, div->nr, div->no, vco_hz, output_hz);
+
+	/* enter slow mode and reset pll */
+	rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
+		     PLL_RESET << PLL_RESET_SHIFT);
+
+	rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
+		     ((div->nr - 1) << PLL_NR_SHIFT) |
+		     ((div->no - 1) << PLL_OD_SHIFT));
+	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
+	udelay(10);
+
+	/* return from reset */
+	rk_clrreg(&pll->con3, PLL_RESET_MASK);
+
+	/* waiting for pll lock */
+	while (!(readl(&pll->con1) & PLL_LOCK_STA))
+		udelay(1);
+
+	rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
+		     PLL_MODE_NORMAL << PLL_MODE_SHIFT);
+
+	return 0;
+}
+
+static void rkclk_init(struct rk3368_cru *cru)
+{
+	u32 apllb, aplll, dpll, cpll, gpll;
+
+	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
+	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
+	rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
+	rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
+
+	apllb = rkclk_pll_get_rate(cru, APLLB);
+	aplll = rkclk_pll_get_rate(cru, APLLL);
+	dpll = rkclk_pll_get_rate(cru, DPLL);
+	cpll = rkclk_pll_get_rate(cru, CPLL);
+	gpll = rkclk_pll_get_rate(cru, GPLL);
+
+	debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
+	       __func__, apllb, aplll, dpll, cpll, gpll);
+}
+
+static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
+{
+	u32 div, con, con_id, rate;
+	u32 pll_rate;
+
+	switch (clk_id) {
+	case SCLK_SDMMC:
+		con_id = 50;
+		break;
+	case SCLK_EMMC:
+		con_id = 51;
+		break;
+	case SCLK_SDIO0:
+		con_id = 48;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	con = readl(&cru->clksel_con[con_id]);
+	switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
+	case MMC_PLL_SEL_GPLL:
+		pll_rate = rkclk_pll_get_rate(cru, GPLL);
+		break;
+	case MMC_PLL_SEL_24M:
+		pll_rate = OSC_HZ;
+		break;
+	case MMC_PLL_SEL_CPLL:
+	case MMC_PLL_SEL_USBPHY_480M:
+	default:
+		return -EINVAL;
+	}
+	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
+	rate = DIV_TO_RATE(pll_rate, div);
+
+	return rate >> 1;
+}
+
+static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
+				ulong clk_id, ulong rate)
+{
+	u32 div;
+	u32 con_id;
+	u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
+
+	div = RATE_TO_DIV(gpll_rate, rate << 1);
+
+	switch (clk_id) {
+	case SCLK_SDMMC:
+		con_id = 50;
+		break;
+	case SCLK_EMMC:
+		con_id = 51;
+		break;
+	case SCLK_SDIO0:
+		con_id = 48;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (div > 0x3f) {
+		div = RATE_TO_DIV(OSC_HZ, rate);
+		rk_clrsetreg(&cru->clksel_con[con_id],
+			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+			     (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
+			     (div << MMC_CLK_DIV_SHIFT));
+	} else {
+		rk_clrsetreg(&cru->clksel_con[con_id],
+			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+			     (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
+			     div << MMC_CLK_DIV_SHIFT);
+	}
+
+	return rk3368_mmc_get_clk(cru, clk_id);
+}
+
+static ulong rk3368_clk_get_rate(struct clk *clk)
+{
+	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate = 0;
+
+	debug("%s id:%ld\n", __func__, clk->id);
+	switch (clk->id) {
+	case HCLK_SDMMC:
+	case HCLK_EMMC:
+		rate = rk3368_mmc_get_clk(priv->cru, clk->id);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong ret = 0;
+
+	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
+	switch (clk->id) {
+	case SCLK_SDMMC:
+	case SCLK_EMMC:
+		ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return ret;
+}
+
+static struct clk_ops rk3368_clk_ops = {
+	.get_rate = rk3368_clk_get_rate,
+	.set_rate = rk3368_clk_set_rate,
+};
+
+static int rk3368_clk_probe(struct udevice *dev)
+{
+	struct rk3368_clk_priv *priv = dev_get_priv(dev);
+
+	rkclk_init(priv->cru);
+
+	return 0;
+}
+
+static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk3368_clk_priv *priv = dev_get_priv(dev);
+
+	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
+
+	return 0;
+}
+
+static int rk3368_clk_bind(struct udevice *dev)
+{
+	int ret;
+
+	/* The reset driver does not have a device node, so bind it here */
+	ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
+	if (ret)
+		error("bind RK3368 reset driver failed: ret=%d\n", ret);
+
+	return ret;
+}
+
+static const struct udevice_id rk3368_clk_ids[] = {
+	{ .compatible = "rockchip,rk3368-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_cru) = {
+	.name		= "rockchip_rk3368_cru",
+	.id		= UCLASS_CLK,
+	.of_match	= rk3368_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct rk3368_cru),
+	.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
+	.ops		= &rk3368_clk_ops,
+	.bind		= rk3368_clk_bind,
+	.probe		= rk3368_clk_probe,
+};
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
new file mode 100644
index 0000000000..0a3ba3bff9
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rv1108.h>
+#include <asm/arch/hardware.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rv1108-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	VCO_MAX_HZ	= 2400U * 1000000,
+	VCO_MIN_HZ	= 600 * 1000000,
+	OUTPUT_MAX_HZ	= 2400U * 1000000,
+	OUTPUT_MIN_HZ	= 24 * 1000000,
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+	((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+	.refdiv = _refdiv,\
+	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
+	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
+	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
+			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
+			 #hz "Hz cannot be hit with PLL "\
+			 "divisors on line " __stringify(__LINE__));
+
+/* use interge mode*/
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+
+static inline int rv1108_pll_id(enum rk_clk_id clk_id)
+{
+	int id = 0;
+
+	switch (clk_id) {
+	case CLK_ARM:
+	case CLK_DDR:
+		id = clk_id - 1;
+		break;
+	case CLK_GENERAL:
+		id = 2;
+		break;
+	default:
+		printf("invalid pll id:%d\n", clk_id);
+		id = -1;
+		break;
+	}
+
+	return id;
+}
+
+static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
+				   enum rk_clk_id clk_id)
+{
+	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
+	uint32_t con0, con1, con3;
+	int pll_id = rv1108_pll_id(clk_id);
+	struct rv1108_pll *pll = &cru->pll[pll_id];
+	uint32_t freq;
+
+	con3 = readl(&pll->con3);
+
+	if (con3 & WORK_MODE_MASK) {
+		con0 = readl(&pll->con0);
+		con1 = readl(&pll->con1);
+		fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
+		postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
+		postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
+		refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT;
+		freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
+	} else {
+		freq = OSC_HZ;
+	}
+
+	return freq;
+}
+
+static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
+{
+	uint32_t con = readl(&cru->clksel_con[24]);
+	ulong pll_rate;
+	uint8_t div;
+
+	if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
+		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
+	else
+		pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
+
+	/*default set 50MHZ for gmac*/
+	if (!rate)
+		rate = 50000000;
+
+	div = DIV_ROUND_UP(pll_rate, rate) - 1;
+	if (div <= 0x1f)
+		rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
+			     div << MAC_CLK_DIV_SHIFT);
+	else
+		debug("Unsupported div for gmac:%d\n", div);
+
+	return DIV_TO_RATE(pll_rate, div);
+}
+
+static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
+{
+	u32 con = readl(&cru->clksel_con[27]);
+	u32 pll_rate;
+	u32 div;
+
+	if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
+		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
+	else
+		pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
+
+	div = DIV_ROUND_UP(pll_rate, rate) - 1;
+	if (div <= 0x3f)
+		rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
+			     div << SFC_CLK_DIV_SHIFT);
+	else
+		debug("Unsupported sfc clk rate:%d\n", rate);
+
+	return DIV_TO_RATE(pll_rate, div);
+}
+
+static ulong rv1108_clk_get_rate(struct clk *clk)
+{
+	struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case 0 ... 63:
+		return rkclk_pll_get_rate(priv->cru, clk->id);
+	default:
+		return -ENOENT;
+	}
+}
+
+static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong new_rate;
+
+	switch (clk->id) {
+	case SCLK_MAC:
+		new_rate = rv1108_mac_set_clk(priv->cru, rate);
+		break;
+	case SCLK_SFC:
+		new_rate = rv1108_sfc_set_clk(priv->cru, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
+static const struct clk_ops rv1108_clk_ops = {
+	.get_rate	= rv1108_clk_get_rate,
+	.set_rate	= rv1108_clk_set_rate,
+};
+
+static void rkclk_init(struct rv1108_cru *cru)
+{
+	unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM);
+	unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR);
+	unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
+
+	rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
+		     0 << MAC_CLK_DIV_SHIFT);
+
+	printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
+}
+
+static int rv1108_clk_probe(struct udevice *dev)
+{
+	struct rv1108_clk_priv *priv = dev_get_priv(dev);
+
+	priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev);
+
+	rkclk_init(priv->cru);
+
+	return 0;
+}
+
+static int rv1108_clk_bind(struct udevice *dev)
+{
+	int ret;
+
+	/* The reset driver does not have a device node, so bind it here */
+	ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev);
+	if (ret)
+		error("No Rv1108 reset driver: ret=%d\n", ret);
+
+	return 0;
+}
+
+static const struct udevice_id rv1108_clk_ids[] = {
+	{ .compatible = "rockchip,rv1108-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_rv1108) = {
+	.name		= "clk_rv1108",
+	.id		= UCLASS_CLK,
+	.of_match	= rv1108_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
+	.ops		= &rv1108_clk_ops,
+	.bind		= rv1108_clk_bind,
+	.probe		= rv1108_clk_probe,
+};