diff options
| author | Tom Rini <trini@konsulko.com> | 2017-06-23 11:02:21 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-06-23 11:02:21 -0400 |
| commit | 7df4ff2c2689a6d3c16eb0c3cce098fcac622b0c (patch) | |
| tree | d24a7f840548d90d159fce2dba61738997ab518d /drivers/clk/rockchip | |
| parent | 72fa58931e1e7feef7801b92671c545c7aca32f1 (diff) | |
| parent | 6a464d9cab63f5317bc914e2de52a4de98377743 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3036.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 28652df72d..5ecf5129d8 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -40,7 +40,7 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); -/* use interge mode*/ +/* use integer mode*/ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); @@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); - /* use interger mode */ - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + /* use integer mode */ + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, |