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authorJagan Teki <jagan@amarulasolutions.com>2020-05-26 11:32:07 +0800
committerKever Yang <kever.yang@rock-chips.com>2020-05-29 18:08:49 +0800
commite1b413d1a9c8b733603ec3249715597a90a43b9d (patch)
treed0a6c8fde3c5533758209c7fc5565df40521a583 /drivers/clk/rockchip
parent80e191119eb73475802ec101ed006bde625c6efd (diff)
clk: rk3399: Enable/Disable TCPHY clocks
Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index ce163aec5a..22c373a623 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1147,6 +1147,18 @@ static int rk3399_clk_enable(struct clk *clk)
case HCLK_HOST1_ARB:
rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
break;
+ case SCLK_UPHY0_TCPDPHY_REF:
+ rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
+ break;
+ case SCLK_UPHY0_TCPDCORE:
+ rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
+ break;
+ case SCLK_UPHY1_TCPDPHY_REF:
+ rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
+ break;
+ case SCLK_UPHY1_TCPDCORE:
+ rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
+ break;
case SCLK_PCIEPHY_REF:
rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
break;
@@ -1229,6 +1241,18 @@ static int rk3399_clk_disable(struct clk *clk)
case HCLK_HOST1_ARB:
rk_setreg(&priv->cru->clksel_con[20], BIT(8));
break;
+ case SCLK_UPHY0_TCPDPHY_REF:
+ rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
+ break;
+ case SCLK_UPHY0_TCPDCORE:
+ rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
+ break;
+ case SCLK_UPHY1_TCPDPHY_REF:
+ rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
+ break;
+ case SCLK_UPHY1_TCPDCORE:
+ rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
+ break;
case SCLK_PCIEPHY_REF:
rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
break;