diff options
| author | Anup Patel <Anup.Patel@wdc.com> | 2019-06-25 06:31:30 +0000 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-07-19 14:24:51 +0800 |
| commit | 8633edeb2a1de97f03cededf3c7fc8956bcec61e (patch) | |
| tree | fb4cf862f428c3c486ba3c0b4bffd43eae46544f /drivers/clk/sifive/Kconfig | |
| parent | ed0ef3776c209c5aefdb0bdf808a3dbdbccd1182 (diff) | |
clk: sifive: Drop GEMGXL clock driver
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/clk/sifive/Kconfig')
| -rw-r--r-- | drivers/clk/sifive/Kconfig | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index d90be1943f..c4d0a1f9b1 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -14,10 +14,3 @@ config CLK_SIFIVE_FU540_PRCI Supports the Power Reset Clock interface (PRCI) IP block found in FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, enable this driver. - -config CLK_SIFIVE_GEMGXL_MGMT - bool "GEMGXL management for SiFive FU540 SoCs" - depends on CLK_SIFIVE - help - Supports the GEMGXL management IP block found in FU540 SoCs to - control GEM TX clock operation mode for 10/100/1000 Mbps. |