diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-12-30 21:29:24 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 22:19:09 +0530 |
| commit | 4acc71193004d2a7eb21a2672ed1822be9007c77 (patch) | |
| tree | ee9b6597621711f5a8b28d18d96eb6eafca0ee09 /drivers/clk/sunxi/clk_a64.c | |
| parent | 6239a6d0920a767a32c1384d0aca10648fa37270 (diff) | |
clk: sunxi: Implement UART clocks
Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_a64.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_a64.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index eb0a45d97f..63424a9e2d 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -19,6 +19,12 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), |