diff options
author | Jagan Teki <jagan@amarulasolutions.com> | 2018-08-02 23:33:55 +0530 |
---|---|---|
committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 22:19:09 +0530 |
commit | 03d87f5909f59523e82d6b77b7b5bcd2054547d4 (patch) | |
tree | 5c4ab62e97545a03ed6e1001fe850aa46cc1ba4d /drivers/clk/sunxi/clk_a83t.c | |
parent | 3ab029368a89391525fbb335fba3c8fb355a44f8 (diff) |
clk: sunxi: Add Allwinner A83T CLK driver
Add initial clock driver for Allwinner A83T.
- Implement USB bus and USB clocks via ccu_clk_gate table
for A83T, so it can accessed in common clk enable and
disable functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset table
for A83T, so it can accessed in common reset deassert
and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_a83t.c')
-rw-r--r-- | drivers/clk/sunxi/clk_a83t.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c new file mode 100644 index 0000000000..3160f7f700 --- /dev/null +++ b/drivers/clk/sunxi/clk_a83t.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun8i-a83t-ccu.h> +#include <dt-bindings/reset/sun8i-a83t-ccu.h> + +static struct ccu_clk_gate a83t_gates[] = { + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), + [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), + [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), + + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), + [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), + [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), + [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)), + [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), +}; + +static struct ccu_reset a83t_resets[] = { + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), + [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), + [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), + [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), +}; + +static const struct ccu_desc a83t_ccu_desc = { + .gates = a83t_gates, + .resets = a83t_resets, +}; + +static int a83t_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets)); +} + +static const struct udevice_id a83t_clk_ids[] = { + { .compatible = "allwinner,sun8i-a83t-ccu", + .data = (ulong)&a83t_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_a83t) = { + .name = "sun8i_a83t_ccu", + .id = UCLASS_CLK, + .of_match = a83t_clk_ids, + .priv_auto_alloc_size = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = a83t_clk_bind, +}; |