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authorTom Rini <trini@konsulko.com>2019-01-24 15:30:48 -0500
committerTom Rini <trini@konsulko.com>2019-01-24 15:30:48 -0500
commitd01806a8fcbdaedcc67cead56ece572021d97ab7 (patch)
tree8c893de10b80db16e01c2253a7cbb0a955123b76 /drivers/clk/sunxi/clk_a83t.c
parent68489ed037530ec29fc0bc452ad6e4b0c5db02ec (diff)
parent543049ab590620a91b37fa0296edd3bcddd0eba2 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'drivers/clk/sunxi/clk_a83t.c')
-rw-r--r--drivers/clk/sunxi/clk_a83t.c75
1 files changed, 75 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
new file mode 100644
index 0000000000..1ef6ac5b25
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
+
+static struct ccu_clk_gate a83t_gates[] = {
+ [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
+ [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
+ [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+
+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
+ [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
+ [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
+ [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
+ [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
+
+ [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
+ [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
+ [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
+ [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
+ [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
+};
+
+static struct ccu_reset a83t_resets[] = {
+ [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
+ [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
+ [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
+
+ [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+ [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
+ [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
+ [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+
+ [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
+};
+
+static const struct ccu_desc a83t_ccu_desc = {
+ .gates = a83t_gates,
+ .resets = a83t_resets,
+};
+
+static int a83t_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
+}
+
+static const struct udevice_id a83t_clk_ids[] = {
+ { .compatible = "allwinner,sun8i-a83t-ccu",
+ .data = (ulong)&a83t_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun8i_a83t) = {
+ .name = "sun8i_a83t_ccu",
+ .id = UCLASS_CLK,
+ .of_match = a83t_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = a83t_clk_bind,
+};