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| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-12-30 21:37:31 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 22:19:09 +0530 |
| commit | 8606f960d4e40f1fbd7fb7e1be30c924dbb9dba0 (patch) | |
| tree | 1a4d280a42846a742a33c8218c35e8ff2b023c36 /drivers/clk/sunxi/clk_v3s.c | |
| parent | 4acc71193004d2a7eb21a2672ed1822be9007c77 (diff) | |
clk: sunxi: Implement UART resets
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_v3s.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_v3s.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index a268786b2d..25ad87500e 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -26,6 +26,10 @@ static struct ccu_reset v3s_resets[] = { [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), + [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), + [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), }; static const struct ccu_desc v3s_ccu_desc = { |