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authorTom Rini <trini@konsulko.com>2017-09-01 10:32:35 -0400
committerTom Rini <trini@konsulko.com>2017-09-01 10:32:35 -0400
commite4adc8ed3c684f41a307fde275e683a391f2a7ce (patch)
treefb6f32cbdce3cd231c7b5e4ab0aceed2198da499 /drivers/clk/uniphier/clk-uniphier-core.c
parent9ec61dbc801761374466e0c8393faaa1e7705520 (diff)
parent0cc0c544bc317548885721d2312c90185642f98c (diff)
Merge git://git.denx.de/u-boot-uniphier
- add {ofnode,dev}_read_resource_byname - provide DT probe hook to Denali NAND driver - update clk/reset driver - update DT - misc cleanups
Diffstat (limited to 'drivers/clk/uniphier/clk-uniphier-core.c')
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index eed21b9a68..722cd6b060 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -146,6 +146,36 @@ static int uniphier_clk_probe(struct udevice *dev)
}
static const struct udevice_id uniphier_clk_match[] = {
+ /* System clock */
+ {
+ .compatible = "socionext,uniphier-ld4-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-clock",
+ .data = (ulong)&uniphier_pxs2_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-clock",
+ .data = (ulong)&uniphier_ld20_sys_clk_data,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-clock",
+ .data = (ulong)&uniphier_ld20_sys_clk_data,
+ },
+ /* Media I/O clock */
{
.compatible = "socionext,uniphier-ld4-mio-clock",
.data = (ulong)&uniphier_mio_clk_data,