diff options
author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-02 21:11:32 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-14 16:36:13 +0900 |
commit | 48264d9beba2ccc18b9497944048eea135883529 (patch) | |
tree | 165956e2eae989ea4ca52144aad1aabf9a7bdb8d /drivers/clk/uniphier/clk-uniphier-mio.c | |
parent | fec4816387a978e651da74c83bcdd5019a6d024c (diff) |
clk: uniphier: add Media I/O clock driver for UniPhier SoCs
This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/clk/uniphier/clk-uniphier-mio.c')
-rw-r--r-- | drivers/clk/uniphier/clk-uniphier-mio.c | 178 |
1 files changed, 178 insertions, 0 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c new file mode 100644 index 0000000000..d91ae34da1 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <clk.h> +#include <dm/device.h> + +#include "clk-uniphier.h" + +#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x20 + 0x200 * (ch), \ + .mask = 0x00000100, \ + .data = 0x00000100, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = 0x00000001, \ + .data = 0x00000001, \ + } + +#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00000000, \ + .rate = 44444444, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00010000, \ + .rate = 33333333, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00020000, \ + .rate = 50000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00020000, \ + .rate = 66666666, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001000, \ + .rate = 100000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001100, \ + .rate = 40000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001200, \ + .rate = 25000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x30 + 0x200 * (ch), \ + .mask = 0x00031300, \ + .data = 0x00001300, \ + .rate = 22222222, \ + } + +#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \ + { \ + .index = (idx), \ + .reg = 0x20 + 0x200 * (ch), \ + .mask = 0x30000000, \ + .data = 0x30000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110 + 0x200 * (ch), \ + .mask = 0x01000000, \ + .data = 0x01000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x114 + 0x200 * (ch), \ + .mask = 0x00000001, \ + .data = 0x00000001, \ + } + +#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \ + { \ + .index = (idx), \ + .reg = 0x20, \ + .mask = 0x02000000, \ + .data = 0x02000000, \ + }, \ + { \ + .index = (idx), \ + .reg = 0x110, \ + .mask = 0x00020000, \ + .data = 0x00020000, \ + } + +static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { + UNIPHIER_MIO_CLK_GATE_SD(0, 0), + UNIPHIER_MIO_CLK_GATE_SD(1, 1), + UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_MIO_CLK_GATE_USB(0, 3), + UNIPHIER_MIO_CLK_GATE_USB(1, 4), + UNIPHIER_MIO_CLK_GATE_USB(2, 5), + UNIPHIER_MIO_CLK_GATE_DMAC(6), + UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */ +}; + +static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = { + UNIPHIER_MIO_CLK_RATE_SD(0, 0), + UNIPHIER_MIO_CLK_RATE_SD(1, 1), + UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */ +}; + +static struct uniphier_clk_soc_data uniphier_mio_clk_data = { + .gate = uniphier_mio_clk_gate, + .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate), + .rate = uniphier_mio_clk_rate, + .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate), +}; + +static const struct udevice_id uniphier_mio_clk_match[] = { + { + .compatible = "socionext,ph1-sld3-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-ld4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro4-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-sld8-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,ph1-pro5-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { + .compatible = "socionext,proxstream2-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(uniphier_mio_clk) = { + .name = "uniphier-mio-clk", + .id = UCLASS_CLK, + .of_match = uniphier_mio_clk_match, + .probe = uniphier_clk_probe, + .remove = uniphier_clk_remove, + .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), + .ops = &uniphier_clk_ops, +}; |