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authorPatrice Chotard <patrice.chotard@st.com>2018-01-18 14:10:05 +0100
committerTom Rini <trini@konsulko.com>2018-01-28 09:39:15 -0500
commit20fe38e75abcf67488b88dd04d3febf13c9d0715 (patch)
tree3464baa7bb585da850cb900b37bd23441bb605d1 /drivers/clk
parent68a69ed2a41551063f012e1ef5f18f2eb4d07f34 (diff)
clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()
Move SYSCFG clock setup into configure_clocks() instead of calling clock_setup() from board file. As this clock is only needed in case of ethernet enabled and as both stm32f4 and stm32f7 are using the Designware ethernet IP, we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed. Move the RMII setup from board_early_init_f() to board_init() to insure that RMII bit is set only when clock driver is initialized. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk_stm32f.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 2187be8cc8..8d0f9d4266 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -67,8 +67,6 @@
#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
-#define RCC_APB2ENR_SAI1EN BIT(22)
-
/*
* RCC AHB1ENR specific definitions
*/
@@ -86,9 +84,9 @@
* RCC APB2ENR specific definitions
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
+#define RCC_APB2ENR_SAI1EN BIT(22)
enum periph_clock {
- SYSCFG_CLOCK_CFG,
TIMER2_CLOCK_CFG,
};
@@ -226,6 +224,11 @@ static int configure_clocks(struct udevice *dev)
/* gate the SAI clock, needed for MMC 1&2 clocks */
setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);
+#ifdef CONFIG_ETH_DESIGNWARE
+ /* gate the SYSCFG clock, needed to set RMII ethernet interface */
+ setbits_le32(&regs->apb2enr, RCC_APB2ENR_SYSCFGEN);
+#endif
+
return 0;
}
@@ -351,9 +354,6 @@ static int stm32_clk_enable(struct clk *clk)
void clock_setup(int peripheral)
{
switch (peripheral) {
- case SYSCFG_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN);
- break;
case TIMER2_CLOCK_CFG:
setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
break;