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authorLionel Debieve <lionel.debieve@st.com>2020-04-24 15:47:57 +0200
committerPatrick Delaunay <patrick.delaunay@st.com>2020-05-14 09:02:12 +0200
commit36911fca63162d8309c2bc6443028b56a6411870 (patch)
treec1d4fdc0c212b63fd404eadce061b07b2b255859 /drivers/clk
parentd7244e4a1fe72c9fbd63f74489099051887b2e89 (diff)
clk: stm32mp1: fix CK_MPU calculation
When the CK_MPU used PLL1_MPUDIV, the current rate is wrong. The clock must use stm32mp1_mpu_div as a shift value. Fix the check value used to enter PLL_MPUDIV. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk_stm32mp1.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 50df8425bf..0d0ea43fd2 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -954,10 +954,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
case RCC_MPCKSELR_PLL:
case RCC_MPCKSELR_PLL_MPUDIV:
clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
- if (p == RCC_MPCKSELR_PLL_MPUDIV) {
+ if ((reg & RCC_SELR_SRC_MASK) ==
+ RCC_MPCKSELR_PLL_MPUDIV) {
reg = readl(priv->base + RCC_MPCKDIVR);
- clock /= stm32mp1_mpu_div[reg &
- RCC_MPUDIV_MASK];
+ clock >>= stm32mp1_mpu_div[reg &
+ RCC_MPUDIV_MASK];
}
break;
}