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authorTom Rini <trini@konsulko.com>2017-08-21 07:16:16 -0400
committerTom Rini <trini@konsulko.com>2017-08-21 07:16:16 -0400
commit8197d92843952b376915fdbcbf67c723feab1532 (patch)
treeda0c744f5254b549498293dc2e148c59af0b9f8d /drivers/clk
parent2d7cb5b426e7e0cdf684d7f8029ad132d7a8d383 (diff)
parent3444d1d40e9ee42ba7423f4fa6651703a8666bc1 (diff)
Merge git://git.denx.de/u-boot-uniphier
- Fix unmet direct dependencies warning - Remove old sLD3 SoC support - Update reset data - Add dr_mode DT property to avoid warning
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/uniphier/Kconfig5
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c4
-rw-r--r--drivers/clk/uniphier/clk-uniphier-mio.c2
3 files changed, 2 insertions, 9 deletions
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index da3e355389..3666d8414c 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -1,9 +1,8 @@
config CLK_UNIPHIER
- bool "Clock driver for UniPhier SoCs"
+ def_bool y
depends on ARCH_UNIPHIER
select CLK
- select SPL_CLK
- default y
+ select SPL_CLK if SPL
help
Support for clock controllers on UniPhier SoCs.
Say Y if you want to control clocks provided by System Control
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 0fb48541b9..eed21b9a68 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -147,10 +147,6 @@ static int uniphier_clk_probe(struct udevice *dev)
static const struct udevice_id uniphier_clk_match[] = {
{
- .compatible = "socionext,uniphier-sld3-mio-clock",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
.compatible = "socionext,uniphier-ld4-mio-clock",
.data = (ulong)&uniphier_mio_clk_data,
},
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 18e6856709..9c13dcd555 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -64,11 +64,9 @@ static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
UNIPHIER_MIO_CLK_USB2(8, 0),
UNIPHIER_MIO_CLK_USB2(9, 1),
UNIPHIER_MIO_CLK_USB2(10, 2),
- UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
- UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
UNIPHIER_CLK_END
};