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authorTom Rini <trini@konsulko.com>2020-08-04 11:07:16 -0400
committerTom Rini <trini@konsulko.com>2020-08-04 11:07:16 -0400
commitbb3694d5b14c891032864dcd44ae261fe595bb0c (patch)
treebefcb69ed2e827e8f68d7c8fb400c6a8b22b967c /drivers/clk
parentd6faedca7670a0b4862cace2f3189998cbec87d8 (diff)
parentd071ff012e0b3f9e77b54340c96f624d6f115782 (diff)
Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips
- doc: fix qemu-mips build instructions - MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/Kconfig7
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk_octeon.c72
3 files changed, 80 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 82cb1874e1..6003e140b5 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -83,6 +83,13 @@ config CLK_INTEL
set up by U-Boot itself but only statically. Thus the driver does not
support changing clock rates, only querying them.
+config CLK_OCTEON
+ bool "Clock controller driver for Marvell MIPS Octeon"
+ depends on CLK && ARCH_OCTEON
+ default y
+ help
+ Enable this to support the clocks on Octeon MIPS platforms.
+
config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d911954581..cda4b4b605 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
+obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
diff --git a/drivers/clk/clk_octeon.c b/drivers/clk/clk_octeon.c
new file mode 100644
index 0000000000..fd559e05fc
--- /dev/null
+++ b/drivers/clk/clk_octeon.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/octeon-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct octeon_clk_priv {
+ u64 core_clk;
+ u64 io_clk;
+};
+
+static int octeon_clk_enable(struct clk *clk)
+{
+ /* Nothing to do on Octeon */
+ return 0;
+}
+
+static ulong octeon_clk_get_rate(struct clk *clk)
+{
+ struct octeon_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case OCTEON_CLK_CORE:
+ return priv->core_clk;
+
+ case OCTEON_CLK_IO:
+ return priv->io_clk;
+
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static struct clk_ops octeon_clk_ops = {
+ .enable = octeon_clk_enable,
+ .get_rate = octeon_clk_get_rate,
+};
+
+static const struct udevice_id octeon_clk_ids[] = {
+ { .compatible = "mrvl,octeon-clk" },
+ { /* sentinel */ }
+};
+
+static int octeon_clk_probe(struct udevice *dev)
+{
+ struct octeon_clk_priv *priv = dev_get_priv(dev);
+
+ /*
+ * The clock values are already read into GD, lets just store them
+ * in priv data
+ */
+ priv->core_clk = gd->cpu_clk;
+ priv->io_clk = gd->bus_clk;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(clk_octeon) = {
+ .name = "clk_octeon",
+ .id = UCLASS_CLK,
+ .of_match = octeon_clk_ids,
+ .ops = &octeon_clk_ops,
+ .probe = octeon_clk_probe,
+ .priv_auto_alloc_size = sizeof(struct octeon_clk_priv),
+};