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authorMarek Vasut <marek.vasut+renesas@gmail.com>2018-05-31 19:25:41 +0200
committerMarek Vasut <marek.vasut+renesas@gmail.com>2018-06-01 09:42:13 +0200
commitf0f1de75c9355aa78c18a1531ad757dcde1fb70e (patch)
tree20636b26a2dd867a0235d2eae029cb49d5879be8 /drivers/clk
parent8376e0e6f74c5e86a821cb81990f2b9429a364f3 (diff)
clk: renesas: Add PLL1 and PLL3 dividers
Add and use the PLL1 and PLL3 dividers. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/renesas/clk-rcar-gen3.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 834cd5ac58..f2550598a4 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -200,9 +200,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL1:
rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
- debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n",
+ rate /= pll_config->pll1_div;
+ debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
- core->parent, pll_config->pll1_mult, rate);
+ core->parent, pll_config->pll1_mult,
+ pll_config->pll1_div, rate);
return rate;
case CLK_TYPE_GEN3_PLL2:
@@ -215,9 +217,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
case CLK_TYPE_GEN3_PLL3:
rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
- debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n",
+ rate /= pll_config->pll3_div;
+ debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
__func__, __LINE__,
- core->parent, pll_config->pll3_mult, rate);
+ core->parent, pll_config->pll3_mult,
+ pll_config->pll3_div, rate);
return rate;
case CLK_TYPE_GEN3_PLL4: