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authorSimon Glass <sjg@chromium.org>2019-09-25 08:55:46 -0600
committerBin Meng <bmeng.cn@gmail.com>2019-10-03 21:10:11 +0800
commite587886a6112e476a74a26e6cf7068a23723097c (patch)
treeae16e247a479c933aeb3df8faba938e75d3a3317 /drivers/core
parentea4316cdb340ce1c05db5d6a869d1840dad68508 (diff)
dm: core: Correct low cell in ofnode_read_pci_addr()
This reads the low cell of the PCI address from the wrong cell. Fix it. Also fix the function that this code came from. Fixes: 9e51204527 (dm: core: Add operations on device tree references) Fixes: 4ea5243a3a (fdt: fix fdtdec_get_pci_addr() for CONFIG_PHYS_64BIT) Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/core')
-rw-r--r--drivers/core/ofnode.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 7eca00cd66..5d47eccf1d 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -617,7 +617,7 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
if ((fdt32_to_cpu(*cell) & type) == type) {
addr->phys_hi = fdt32_to_cpu(cell[0]);
addr->phys_mid = fdt32_to_cpu(cell[1]);
- addr->phys_lo = fdt32_to_cpu(cell[1]);
+ addr->phys_lo = fdt32_to_cpu(cell[2]);
break;
}