ddr: altera: Clean up scc_mgr_set_oct_out1_delay()

Make this function more readable, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>

1 files changed, 14 insertions, 9 deletions

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 0b76ba29db..cc2fa47b2d 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -430,11 +430,19 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 	writel(0, &sdr_scc_mgr->update);
 }
 
-static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
+/**
+ * scc_mgr_set_oct_out1_delay() - Set OCT output delay
+ * @write_group:	Write group
+ * @delay:		Delay value
+ *
+ * This function sets the OCT output delay in SCC manager.
+ */
+static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 {
-	uint32_t read_group;
-	uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
-
+	const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+			  RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+	const int base = write_group * ratio;
+	int i;
 	/*
 	 * Load the setting in the SCC manager
 	 * Although OCT affects only write data, the OCT delay is controlled
@@ -442,11 +450,8 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
 	 * For protocols where a write group consists of multiple read groups,
 	 * the setting must be set multiple times.
 	 */
-	for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-	     RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
-	     read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
-	     RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
-		writel(delay, addr + (read_group << 2));
+	for (i = 0; i < ratio; i++)
+		scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 }
 
 static void scc_mgr_set_hhp_extras(void)