diff options
| author | Marek Vasut <marex@denx.de> | 2015-07-26 11:34:09 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:24 +0200 |
| commit | cbcaf4604329a6a69597630d7abdab942e2c59c8 (patch) | |
| tree | e1cfae9f75ebe330495775839d7db3ec73c249c6 /drivers/ddr/altera | |
| parent | 90a584b76345d95f541e5843aba158ceb28a1271 (diff) | |
ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
Factor out (afi_clocks - 1) into a single place instead of having it
all around the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/ddr/altera')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 5a6c99188a..25de209b5d 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -767,8 +767,10 @@ static void delay_for_n_mem_clocks(const u32 clocks) debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks); - /* scale (rounding up) to get afi clocks */ + /* Scale (rounding up) to get afi clocks. */ afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO); + if (afi_clocks) /* Temporary underflow protection */ + afi_clocks--; /* * Note, we don't bother accounting for being off a little @@ -779,18 +781,18 @@ static void delay_for_n_mem_clocks(const u32 clocks) */ if (afi_clocks == 0) { ; - } else if (afi_clocks <= 0x100) { - inner = afi_clocks - 1; + } else if (afi_clocks < 0x100) { + inner = afi_clocks; outer = 0; c_loop = 0; - } else if (afi_clocks <= 0x10000) { + } else if (afi_clocks < 0x10000) { inner = 0xff; - outer = (afi_clocks - 1) >> 8; + outer = afi_clocks >> 8; c_loop = 0; - } else { + } else { /* >= 0x10000 */ inner = 0xff; outer = 0xff; - c_loop = (afi_clocks - 1) >> 16; + c_loop = afi_clocks >> 16; } /* @@ -810,7 +812,7 @@ static void delay_for_n_mem_clocks(const u32 clocks) * and sequencer rom and keeps the delays more accurate and reduces * overhead */ - if (afi_clocks <= 0x100) { + if (afi_clocks < 0x100) { writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), &sdr_rw_load_mgr_regs->load_cntr1); |