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authorYork Sun <york.sun@nxp.com>2018-01-29 09:44:33 -0800
committerYork Sun <york.sun@nxp.com>2018-01-30 09:14:06 -0800
commit426230a65f2dd62c3b6c1509e9775d5500db20d3 (patch)
tree1f500bcdf25fc0ed2a5840bcdecd558173de9da1 /drivers/ddr/fsl/ddr4_dimm_params.c
parenta9b1c2164a45e0c1af59b8e7a1c92f2f53babe92 (diff)
drivers/ddr/fsl: Fix DDR4 RDIMM support
For DDR4, command/address delay in mode registers and parity latency in timing config register are only needed for UDIMMs, but not RDIMMs. Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix calculation of timing config registers. Use hexadecimal format for printing RCW (register control word) registers. Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/ddr/fsl/ddr4_dimm_params.c')
-rw-r--r--drivers/ddr/fsl/ddr4_dimm_params.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c
index 42834ca7b2..6e26ba88a5 100644
--- a/drivers/ddr/fsl/ddr4_dimm_params.c
+++ b/drivers/ddr/fsl/ddr4_dimm_params.c
@@ -179,6 +179,8 @@ unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
case DDR4_SPD_MODULETYPE_RDIMM:
/* Registered/buffered DIMMs */
pdimm->registered_dimm = 1;
+ if (spd->mod_section.registered.reg_map & 0x1)
+ pdimm->mirrored_dimm = 1;
break;
case DDR4_SPD_MODULETYPE_UDIMM: