diff options
| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-11-21 11:36:48 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-12-05 08:31:45 -0800 |
| commit | 02fb2761576be8096ebf1b3f961a2cdb21b422ae (patch) | |
| tree | 70cd556e7498ef63f2d51519958cfc2994c73950 /drivers/ddr/fsl/fsl_ddr_gen4.c | |
| parent | 5a17b8b5dab8973089b7400d05f8503d56f29370 (diff) | |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/ddr/fsl/fsl_ddr_gen4.c')
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 30f60e0fe1..dadcb3abc3 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -64,9 +64,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #ifdef CONFIG_FSL_DDR_BIST char buffer[CONFIG_SYS_CBSIZE]; #endif -#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) - u32 ddr_freq; -#endif switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; @@ -223,16 +220,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[i], regs->debug[i]); } } -#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 - /* Erratum applies when accumulated ECC is used, or DBI is enabled */ -#define IS_ACC_ECC_EN(v) ((v) & 0x4) -#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) - if (has_erratum_a008378()) { - if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || - IS_DBI(regs->ddr_sdram_cfg_3)) - ddr_setbits32(&ddr->debug[28], 0x9 << 20); - } -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 /* Part 1 of 2 */ @@ -270,19 +257,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], temp32); #endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - temp32 = ddr_in32(&ddr->debug[28]); - if (ddr_freq <= 1333) - ddr_out32(&ddr->debug[28], temp32 | 0x0080006a); - else if (ddr_freq <= 1600) - ddr_out32(&ddr->debug[28], temp32 | 0x0070006f); - else if (ddr_freq <= 1867) - ddr_out32(&ddr->debug[28], temp32 | 0x00700076); - else if (ddr_freq <= 2133) - ddr_out32(&ddr->debug[28], temp32 | 0x0060007b); -#endif - #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 temp32 = get_ddr_freq(ctrl_num) / 1000000; if ((temp32 > 1900) && (temp32 < 2300)) { |