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| author | Stefano Babic <sbabic@denx.de> | 2015-03-02 09:42:53 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-03-02 09:42:53 +0100 |
| commit | b9cb64825b5e6efeb715abd8b48d9b12f98973e9 (patch) | |
| tree | d70d73a986308dee88474572006f5c60b10749be /drivers/ddr/fsl/mpc85xx_ddr_gen3.c | |
| parent | 4579dc37c3cce36d9521c26c6e82881393ec769e (diff) | |
| parent | 1606b34aa50804227806971dbb6b82ea0bf81f55 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'drivers/ddr/fsl/mpc85xx_ddr_gen3.c')
| -rw-r--r-- | drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 8f4d01ad85..6752d4d29e 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -426,7 +426,7 @@ step2: bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; + (get_ddr_freq(ctrl_num) >> 20)) << 1; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 timeout_save = timeout; #endif @@ -538,12 +538,14 @@ step2: case 1: out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); break; +#if CONFIG_CHIP_SELECTS_PER_CTRL > 2 case 2: out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); break; case 3: out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); break; +#endif } clrbits_be32(&ddr->sdram_cfg, 0x2); } |