diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2019-08-08 09:59:08 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-10-08 16:36:37 +0200 |
| commit | 825ab6b406cba74ae63a1e3373c2f0b62b855f08 (patch) | |
| tree | 2177aa058484bc3c7c787bff027e12d9882601ab /drivers/ddr/imx/imx8m/helper.c | |
| parent | 7b14cc991ba85d2b035479177cc1391ed729abd3 (diff) | |
driver: ddr: Refine the ddr init driver on imx8m
Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr/imx/imx8m/helper.c')
| -rw-r--r-- | drivers/ddr/imx/imx8m/helper.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c index 3e605353ea..b3e63834ca 100644 --- a/drivers/ddr/imx/imx8m/helper.c +++ b/drivers/ddr/imx/imx8m/helper.c @@ -67,7 +67,7 @@ void ddr_load_train_firmware(enum fw_type type) i += 4; } - debug("check ddr4_pmu_train_imem code\n"); + debug("check ddr_pmu_train_imem code\n"); pr_from32 = imem_start; pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; for (i = 0x0; i < IMEM_LEN; ) { @@ -84,9 +84,9 @@ void ddr_load_train_firmware(enum fw_type type) i += 4; } if (error) - printf("check ddr4_pmu_train_imem code fail=%d\n", error); + printf("check ddr_pmu_train_imem code fail=%d\n", error); else - debug("check ddr4_pmu_train_imem code pass\n"); + debug("check ddr_pmu_train_imem code pass\n"); debug("check ddr4_pmu_train_dmem code\n"); pr_from32 = dmem_start; @@ -105,9 +105,9 @@ void ddr_load_train_firmware(enum fw_type type) } if (error) - printf("check ddr4_pmu_train_dmem code fail=%d", error); + printf("check ddr_pmu_train_dmem code fail=%d", error); else - debug("check ddr4_pmu_train_dmem code pass\n"); + debug("check ddr_pmu_train_dmem code pass\n"); } void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, |