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authorChris Packham <judge.packham@gmail.com>2018-01-18 17:16:10 +1300
committerStefan Roese <sr@denx.de>2018-01-19 16:30:29 +0100
commit672e5598301b63f95d7dcceb4436f3cb40643f88 (patch)
treed3bcd98cfca254c60516e15ff4b55ee052510d36 /drivers/ddr/marvell/a38x/ddr3_topology_def.h
parent8bddf678dbe3c766d4f1c242cda3b9e3ed9e2425 (diff)
ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_topology_def.h')
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_topology_def.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_topology_def.h b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
index 64a0447dd1..a17eca0418 100644
--- a/drivers/ddr/marvell/a38x/ddr3_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_topology_def.h
@@ -70,7 +70,8 @@ enum speed_bin_table_elements {
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
- SPEED_BIN_TMOD
+ SPEED_BIN_TMOD,
+ SPEED_BIN_TXPDLL
};
#endif /* _DDR3_TOPOLOGY_DEF_H */