diff options
| author | Chris Packham <judge.packham@gmail.com> | 2018-05-10 13:28:30 +1200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-05-14 10:01:56 +0200 |
| commit | e6f61622d32327907f824154c7f88ddce3c700cc (patch) | |
| tree | da08a5e3e1811a0fda31e4a4e64e37f3318d947d /drivers/ddr/marvell/a38x/ddr3_training.c | |
| parent | 2b4ffbf6b4944a0b3125fd2c9c0ba3568264367a (diff) | |
ARM: mvebu: a38x: restore support for setting timing
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training.c')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 1f26d506da..799c5ba089 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -365,6 +365,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); enum hws_ddr_freq freq = tm->interface_params[0].memory_freq; + enum mv_ddr_timing timing; DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n", @@ -603,8 +604,12 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ DUNIT_CTRL_HIGH_REG, (init_cntr_prm->msys_init << 7), (1 << 7))); + timing = tm->interface_params[if_id].timing; + if (mode_2t != 0xff) { t2t = mode_2t; + } else if (timing != MV_DDR_TIM_DEFAULT) { + t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0; } else { /* calculate number of CS (per interface) */ CHECK_STATUS(calc_cs_num @@ -1268,6 +1273,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); unsigned int tclk; + enum mv_ddr_timing timing = tm->interface_params[if_id].timing; DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("dev %d access %d IF %d freq %d\n", dev_num, @@ -1410,6 +1416,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, /* Calculate 2T mode */ if (mode_2t != 0xff) { t2t = mode_2t; + } else if (timing != MV_DDR_TIM_DEFAULT) { + t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0; } else { /* Calculate number of CS per interface */ CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num)); |