diff options
| author | Chris Packham <judge.packham@gmail.com> | 2018-01-18 17:16:10 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-01-19 16:30:29 +0100 |
| commit | 672e5598301b63f95d7dcceb4436f3cb40643f88 (patch) | |
| tree | d3bcd98cfca254c60516e15ff4b55ee052510d36 /drivers/ddr/marvell/a38x/ddr3_training_db.c | |
| parent | 8bddf678dbe3c766d4f1c242cda3b9e3ed9e2425 (diff) | |
ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_db.c')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_db.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c index 861dfb19c3..0e11b434ab 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_db.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c @@ -152,18 +152,18 @@ u8 twr_mask_table[] = { 10, 10, 10, - 1, /*5 */ - 2, /*6 */ - 3, /*7 */ + 1, /*5*/ + 2, /*6*/ + 3, /*7*/ + 4, /*8*/ 10, + 5, /*10*/ 10, - 5, /*10 */ + 6, /*12*/ 10, - 6, /*12 */ + 7, /*14*/ 10, - 7, /*14 */ - 10, - 0 /*16 */ + 0 /*16*/ }; u8 cl_mask_table[] = { @@ -431,6 +431,9 @@ u32 speed_bin_table(u8 index, enum speed_bin_table_elements element) case SPEED_BIN_TMOD: result = 15000; break; + case SPEED_BIN_TXPDLL: + result = 24000; + break; default: break; } |