diff options
author | Chris Packham <judge.packham@gmail.com> | 2018-05-10 13:28:29 +1200 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2018-05-14 10:01:56 +0200 |
commit | 2b4ffbf6b4944a0b3125fd2c9c0ba3568264367a (patch) | |
tree | dc75d0e07677505b8611a670483a349f214c9e75 /drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h | |
parent | 00a7767766ace1f3ca3de7f9d44e145b9092bbad (diff) |
ARM: mvebu: a38x: sync ddr training code with upstream
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT
INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.
Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h')
-rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h index 1d7af4dcd3..38058cba8a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h @@ -45,9 +45,13 @@ int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, u32 cs_num); int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, u32 mode); +int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num, + u32 direction, u32 mode); int ddr3_tip_print_regs(u32 dev_num); int ddr3_tip_reg_dump(u32 dev_num); int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type, u32 burst_length); - +int mv_ddr_dm_to_dq_diff_get(u8 adll_byte_high, u8 adll_byte_low, u8 *vw_vector, + int *delta_h_adll, int *delta_l_adll); +int mv_ddr_dm_vw_get(enum hws_pattern pattern, u32 cs, u8 *vw_vector); #endif /* _DDR3_TRAINING_IP_BIST_H_ */ |