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| author | Tom Rini <trini@konsulko.com> | 2018-12-09 08:40:49 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-09 08:40:49 -0500 |
| commit | 8cb8c0c6a83bef319023ac2e967a85e1e92e18bc (patch) | |
| tree | e76bc8071eab1a08ad92f30cc4ea4ad92597fb42 /drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h | |
| parent | 51c2345bd24837f9f67f16268da6dc71573f1325 (diff) | |
| parent | 5ca84c6dd2b3060471171cce3f76d8af35060c0b (diff) | |
Merge git://git.denx.de/u-boot-marvell
- Sync DDR training with Marvell code for Armada 38x by Chris
- Misc updates to Armada 38x Helios4 board by Aditya
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h index f614d688c9..2df592e1b0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h @@ -28,15 +28,15 @@ typedef int (*HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR)( u8 dev_num, enum hws_access_type interface_access, u32 if_id, u32 offset, u32 data, u32 mask); typedef int (*HWS_TIP_GET_FREQ_CONFIG_INFO)( - u8 dev_num, enum hws_ddr_freq freq, + u8 dev_num, enum mv_ddr_freq freq, struct hws_tip_freq_config_info *freq_config_info); typedef int (*HWS_TIP_GET_DEVICE_INFO)( u8 dev_num, struct ddr3_device_info *info_ptr); typedef int (*HWS_GET_CS_CONFIG_FUNC_PTR)( u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info); typedef int (*HWS_SET_FREQ_DIVIDER_FUNC_PTR)( - u8 dev_num, u32 if_id, enum hws_ddr_freq freq); -typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq); + u8 dev_num, u32 if_id, enum mv_ddr_freq freq); +typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq); typedef int (*HWS_TRAINING_IP_IF_WRITE_FUNC_PTR)( u32 dev_num, enum hws_access_type access_type, u32 dunit_id, u32 reg_addr, u32 data, u32 mask); @@ -54,7 +54,7 @@ typedef int (*HWS_TRAINING_IP_ALGO_RUN_FUNC_PTR)( u32 dev_num, enum hws_algo_type algo_type); typedef int (*HWS_TRAINING_IP_SET_FREQ_FUNC_PTR)( u32 dev_num, enum hws_access_type access_type, u32 if_id, - enum hws_ddr_freq frequency); + enum mv_ddr_freq frequency); typedef int (*HWS_TRAINING_IP_INIT_CONTROLLER_FUNC_PTR)( u32 dev_num, struct init_cntr_param *init_cntr_prm); typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num); @@ -64,7 +64,7 @@ typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)( typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)( u32 dev_num, struct mv_ddr_topology_map *tm); typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)( - u32 dev_num, enum hws_ddr_freq frequency, + u32 dev_num, enum mv_ddr_freq frequency, enum hws_static_config_type static_config_type, u32 if_id); typedef int (*HWS_TRAINING_IP_EXTERNAL_READ_PTR)( u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); |