ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").

The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:

  ddr3: add missing txsdll parameter
  ddr3: fix tfaw timimg parameter
  ddr3: fix trrd timimg parameter
  merge ddr3 topology header file with mv_ddr_topology one
  mv_ddr: a38x: fix zero memory size scrubbing issue

The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef

    find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
        xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
                 -UCONFIG_APN806 -UCONFIG_MC_STATIC \
                 -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
                 -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
                 -UA70X0

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 19 insertions, 0 deletions

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_regs.h b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
index ceda204a49..cf2a6c92e8 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_regs.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
@@ -134,6 +134,7 @@
 #define SDRAM_OP_CMD_CS_BASE			8
 #define SDRAM_OP_CMD_CS_OFFS(cs)		(SDRAM_OP_CMD_CS_BASE + (cs))
 #define SDRAM_OP_CMD_CS_MASK			0x1
+#define SDRAM_OP_CMD_ALL_CS_MASK		0xf
 enum {
 	CMD_NORMAL,
 	CMD_PRECHARGE,
@@ -270,6 +271,10 @@ enum {
 #define ZQC_CFG_REG				0x15e4
 #define DRAM_PHY_CFG_REG			0x15ec
 #define ODPG_CTRL_CTRL_REG			0x1600
+#define ODPG_CTRL_AUTO_REFRESH_OFFS		21
+#define ODPG_CTRL_AUTO_REFRESH_MASK		0x1
+#define ODPG_CTRL_AUTO_REFRESH_DIS		1
+#define ODPG_CTRL_AUTO_REFRESH_ENA		0
 
 #define ODPG_DATA_CTRL_REG			0x1630
 #define ODPG_WRBUF_WR_CTRL_OFFS			0
@@ -406,6 +411,20 @@ enum {
 #define CRX_PHY_REG(cs)				(CRX_PHY_BASE + (cs) * 0x4)
 
 #define PHY_CTRL_PHY_REG			0x90
+#define INV_PAD0_OFFS				2
+#define INV_PAD1_OFFS				3
+#define INV_PAD2_OFFS				4
+#define INV_PAD3_OFFS				5
+#define INV_PAD4_OFFS				6
+#define INV_PAD5_OFFS				7
+#define INV_PAD6_OFFS				8
+#define INV_PAD7_OFFS				9
+#define INV_PAD8_OFFS				10
+#define INV_PAD9_OFFS				11
+#define INV_PAD10_OFFS				12
+#define INV_PAD_MASK				0x1
+#define INVERT_PAD				1
+
 #define ADLL_CFG0_PHY_REG			0x92
 #define ADLL_CFG1_PHY_REG			0x93
 #define ADLL_CFG2_PHY_REG			0x94