diff options
| author | Chris Packham <judge.packham@gmail.com> | 2018-12-03 14:26:49 +1300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2018-12-08 16:19:40 +0100 |
| commit | ebb1a593252205114f6133b898f67473cc4c4899 (patch) | |
| tree | 8a01f4e39a19bcabcf799b0dbf6935f5d0a66619 /drivers/ddr/marvell/a38x/mv_ddr_spd.c | |
| parent | 3589025867274ff28f689029ab8323301771c8ec (diff) | |
ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").
The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:
ddr3: add missing txsdll parameter
ddr3: fix tfaw timimg parameter
ddr3: fix trrd timimg parameter
merge ddr3 topology header file with mv_ddr_topology one
mv_ddr: a38x: fix zero memory size scrubbing issue
The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
-UA70X0
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/marvell/a38x/mv_ddr_spd.c')
| -rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_spd.c | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.c b/drivers/ddr/marvell/a38x/mv_ddr_spd.c index e9e7f18098..04dbfe94d6 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_spd.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.c @@ -81,9 +81,6 @@ int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_ timing_data[MV_DDR_TWR_MIN] = (spd_data->byte_fields.byte_42 + (spd_data->byte_fields.byte_41.bit_fields.t_wr_min_msn << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB; - /* FIXME: wa: set twr to a default value, if it's unset on spd */ - if (timing_data[MV_DDR_TWR_MIN] == 0) - timing_data[MV_DDR_TWR_MIN] = 15000; /* t rcd min, ps */ calc_val = spd_data->byte_fields.byte_25 * MV_DDR_SPD_DATA_MTB + @@ -127,6 +124,13 @@ int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_ return 1; timing_data[MV_DDR_TRRD_L_MIN] = calc_val; + /* t ccd l min, ps */ + calc_val = spd_data->byte_fields.byte_40 * MV_DDR_SPD_DATA_MTB + + (signed char)spd_data->byte_fields.byte_117 * MV_DDR_SPD_DATA_FTB; + if (calc_val < 0) + return 1; + timing_data[MV_DDR_TCCD_L_MIN] = calc_val; + /* t faw min, ps */ timing_data[MV_DDR_TFAW_MIN] = (spd_data->byte_fields.byte_37 + (spd_data->byte_fields.byte_36.bit_fields.t_faw_min_msn << MV_DDR_SPD_MSB_OFFS)) * @@ -136,17 +140,11 @@ int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_ timing_data[MV_DDR_TWTR_S_MIN] = (spd_data->byte_fields.byte_44 + (spd_data->byte_fields.byte_43.bit_fields.t_wtr_s_min_msn << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB; - /* FIXME: wa: set twtr_s to a default value, if it's unset on spd */ - if (timing_data[MV_DDR_TWTR_S_MIN] == 0) - timing_data[MV_DDR_TWTR_S_MIN] = 2500; /* t wtr l min, ps */ timing_data[MV_DDR_TWTR_L_MIN] = (spd_data->byte_fields.byte_45 + (spd_data->byte_fields.byte_43.bit_fields.t_wtr_l_min_msn << MV_DDR_SPD_MSB_OFFS)) * MV_DDR_SPD_DATA_MTB; - /* FIXME: wa: set twtr_l to a default value, if it's unset on spd */ - if (timing_data[MV_DDR_TWTR_L_MIN] == 0) - timing_data[MV_DDR_TWTR_L_MIN] = 7500; return 0; } |