diff options
author | Tom Rini <trini@konsulko.com> | 2020-01-08 15:23:49 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-01-08 15:23:49 -0500 |
commit | ce022f2857714e19c6b31a023b8145782ecef5a5 (patch) | |
tree | c7a3666314cdcb3a2d3ae2a88a579dbf4ebfc3e1 /drivers/ddr | |
parent | 9af51fb3a505f895d64bd1f8a5967bfaa510add4 (diff) | |
parent | 8097aee3abc3b773aceea01f756a38b34b274e1e (diff) |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'drivers/ddr')
-rw-r--r-- | drivers/ddr/altera/Kconfig | 6 | ||||
-rw-r--r-- | drivers/ddr/altera/Makefile | 3 | ||||
-rw-r--r-- | drivers/ddr/altera/sdram_agilex.c | 168 | ||||
-rw-r--r-- | drivers/ddr/altera/sdram_gen5.c | 12 | ||||
-rw-r--r-- | drivers/ddr/altera/sdram_s10.c | 320 | ||||
-rw-r--r-- | drivers/ddr/altera/sdram_s10.h | 148 | ||||
-rw-r--r-- | drivers/ddr/altera/sdram_soc64.c | 305 | ||||
-rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 187 |
8 files changed, 691 insertions, 458 deletions
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b1c1be3b5..8f590dc5f6 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 341ac0d73b..39dfee5d5a 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -9,5 +9,6 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o endif diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c new file mode 100644 index 0000000000..0cbcd14056 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int sdram_mmr_init_full(struct udevice *dev) +{ + struct altera_sdram_platdata *plat = dev->platdata; + struct altera_sdram_priv *priv = dev_get_priv(dev); + u32 i; + int ret; + phys_size_t hw_size; + bd_t bd = {0}; + + /* Ensure HMC clock is running */ + if (poll_hmc_clock_status()) { + debug("DDR: Error as HMC clock was not running\n"); + return -EPERM; + } + + /* Trying 3 times to do a calibration */ + for (i = 0; i < 3; i++) { + ret = wait_for_bit_le32((const void *)(plat->hmc + + DDRCALSTAT), + DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000, + false); + if (!ret) + break; + + emif_reset(plat); + } + + if (ret) { + puts("DDR: Error as SDRAM calibration failed\n"); + return -EPERM; + } + debug("DDR: Calibration success\n"); + + /* + * Configure the DDR IO size + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + /* Configure DDR IO size x16, x32 and x64 mode */ + u32 update_value; + + update_value = hmc_readl(plat, NIOSRESERVED0); + update_value = (update_value & 0xFF) >> 5; + + /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */ + update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); + hmc_ecc_writel(plat, update_value, DDRIOCTRL); + + /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */ + hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH); + + /* assigning the SDRAM size */ + phys_size_t size = sdram_calculate_size(plat); + + if (size <= 0) + hw_size = PHYS_SDRAM_1_SIZE; + else + hw_size = size; + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + puts("DDR: Failed to decode memory node\n"); + return -ENXIO; + } + + if (gd->ram_size != hw_size) { + printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n", + gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + + printf("DDR: %lld MiB\n", gd->ram_size >> 20); + + /* This enables nonsecure access to DDR */ + /* mpuregion0addr_limit */ + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, + FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); + FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); + + /* nonmpuregion0addr_limit */ + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, + FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); + + /* Enable mpuregion0enable and nonmpuregion0enable */ + FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, + FW_MPU_DDR_SCR_EN_SET); + + u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); + + /* Enable or disable the DDR ECC */ + if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { + setbits_le32(plat->hmc + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(plat->hmc + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(plat->hmc + ECCCTRL2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + setbits_le32(plat->hmc + ERRINTEN, + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK); + + if (!cpu_has_been_warmreset()) + sdram_init_ecc_bits(&bd); + } else { + clrbits_le32(plat->hmc + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(plat->hmc + ECCCTRL2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } + + /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + + sdram_size_check(&bd); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + debug("DDR: HMC init success\n"); + return 0; +} diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 8c8ea19eb9..435f42bc0a 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -40,9 +40,6 @@ struct sdram_prot_rule { u32 hi_prot_id; }; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); /** @@ -455,12 +452,14 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; int ret; - writel(rows, &sysmgr_regs->iswgrp_handoff[4]); + writel(rows, + socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4)); sdr_load_regs(sdr_ctrl, cfg); /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); + writel(cfg->fpgaport_rst, + socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3)); /* only enable if the FPGA is programmed */ if (fpgamgr_test_fpga_ready()) { @@ -516,7 +515,8 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) * since the FB specifies we modify ROWBITs to work around SDRAM * controller issue. */ - row = readl(&sysmgr_regs->iswgrp_handoff[4]); + row = readl(socfpga_get_sysmgr_addr() + + SYSMGR_ISWGRP_HANDOFF_OFFSET(4)); if (row == 0) row = rowbits; /* diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 82d9a13efa..93c15dd18b 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -14,32 +14,15 @@ #include <reset.h> #include "sdram_s10.h" #include <wait_bit.h> -#include <asm/arch/firewall_s10.h> -#include <asm/arch/system_manager.h> +#include <asm/arch/firewall.h> #include <asm/arch/reset_manager.h> #include <asm/io.h> #include <linux/sizes.h> -struct altera_sdram_priv { - struct ram_info info; - struct reset_ctl_bulk resets; -}; - -struct altera_sdram_platdata { - void __iomem *hmc; - void __iomem *ddr_sch; - void __iomem *iomhc; -}; - DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_system_manager *sysmgr_regs = - (void *)SOCFPGA_SYSMGR_ADDRESS; - #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) -#define PGTABLE_OFF 0x4000 - /* The followring are the supported configurations */ u32 ddr_config[] = { /* DDR_CONFIG(Address order,Bank,Column,Row) */ @@ -66,28 +49,6 @@ u32 ddr_config[] = { DDR_CONFIG(1, 4, 10, 17), }; -static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) -{ - return readl(plat->iomhc + reg); -} - -static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) -{ - return readl(plat->hmc + reg); -} - -static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, - u32 data, u32 reg) -{ - return writel(data, plat->hmc + reg); -} - -static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, - u32 reg) -{ - return writel(data, plat->ddr_sch + reg); -} - int match_ddr_conf(u32 ddr_conf) { int i; @@ -99,192 +60,12 @@ int match_ddr_conf(u32 ddr_conf) return 0; } -static int emif_clear(struct altera_sdram_platdata *plat) -{ - hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); - - return wait_for_bit_le32((const void *)(plat->hmc + - RSTHANDSHAKESTAT), - DDR_HMC_RSTHANDSHAKE_MASK, - false, 1000, false); -} - -static int emif_reset(struct altera_sdram_platdata *plat) -{ - u32 c2s, s2c, ret; - - c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; - s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; - - debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", - c2s, s2c, hmc_readl(plat, NIOSRESERVED0), - hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2), - hmc_readl(plat, DRAMSTS)); - - if (s2c && emif_clear(plat)) { - printf("DDR: emif_clear() failed\n"); - return -1; - } - - debug("DDR: Triggerring emif reset\n"); - hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); - - /* if seq2core[3] = 0, we are good */ - ret = wait_for_bit_le32((const void *)(plat->hmc + - RSTHANDSHAKESTAT), - DDR_HMC_SEQ2CORE_INT_RESP_MASK, - false, 1000, false); - if (ret) { - printf("DDR: failed to get ack from EMIF\n"); - return ret; - } - - ret = emif_clear(plat); - if (ret) { - printf("DDR: emif_clear() failed\n"); - return ret; - } - - debug("DDR: %s triggered successly\n", __func__); - return 0; -} - -static int poll_hmc_clock_status(void) -{ - return wait_for_bit_le32(&sysmgr_regs->hmc_clk, - SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); -} - -static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) -{ - phys_size_t i; - - if (addr % CONFIG_SYS_CACHELINE_SIZE) { - printf("DDR: address 0x%llx is not cacheline size aligned.\n", - addr); - hang(); - } - - if (size % CONFIG_SYS_CACHELINE_SIZE) { - printf("DDR: size 0x%llx is not multiple of cacheline size\n", - size); - hang(); - } - - /* Use DC ZVA instruction to clear memory to zeros by a cache line */ - for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) { - asm volatile("dc zva, %0" - : - : "r"(addr) - : "memory"); - addr += CONFIG_SYS_CACHELINE_SIZE; - } -} - -static void sdram_init_ecc_bits(bd_t *bd) -{ - phys_size_t size, size_init; - phys_addr_t start_addr; - int bank = 0; - unsigned int start = get_timer(0); - - icache_enable(); - - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; - - /* Initialize small block for page table */ - memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); - gd->arch.tlb_addr = start_addr + PGTABLE_OFF; - gd->arch.tlb_size = PGTABLE_SIZE; - start_addr += PGTABLE_SIZE + PGTABLE_OFF; - size -= (PGTABLE_OFF + PGTABLE_SIZE); - dcache_enable(); - - while (1) { - while (size) { - size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); - sdram_clear_mem(start_addr, size_init); - size -= size_init; - start_addr += size_init; - WATCHDOG_RESET(); - } - - bank++; - if (bank >= CONFIG_NR_DRAM_BANKS) - break; - - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; - } - - dcache_disable(); - icache_disable(); - - printf("SDRAM-ECC: Initialized success with %d ms\n", - (unsigned int)get_timer(start)); -} - -static void sdram_size_check(bd_t *bd) -{ - phys_size_t total_ram_check = 0; - phys_size_t ram_check = 0; - phys_addr_t start = 0; - int bank; - - /* Sanity check ensure correct SDRAM size specified */ - debug("DDR: Running SDRAM size sanity check\n"); - - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = bd->bi_dram[bank].start; - while (ram_check < bd->bi_dram[bank].size) { - ram_check += get_ram_size((void *)(start + ram_check), - (phys_size_t)SZ_1G); - } - total_ram_check += ram_check; - ram_check = 0; - } - - /* If the ram_size is 2GB smaller, we can assume the IO space is - * not mapped in. gd->ram_size is the actual size of the dram - * not the accessible size. - */ - if (total_ram_check != gd->ram_size) { - puts("DDR: SDRAM size check failed!\n"); - hang(); - } - - debug("DDR: SDRAM size check passed!\n"); -} - -/** - * sdram_calculate_size() - Calculate SDRAM size - * - * Calculate SDRAM device size based on SDRAM controller parameters. - * Size is specified in bytes. - */ -static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) -{ - u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); - - size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & - DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); - - return size; -} - /** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * * Initialize the SDRAM MMR. */ -static int sdram_mmr_init_full(struct udevice *dev) +int sdram_mmr_init_full(struct udevice *dev) { struct altera_sdram_platdata *plat = dev->platdata; struct altera_sdram_priv *priv = dev_get_priv(dev); @@ -324,6 +105,20 @@ static int sdram_mmr_init_full(struct udevice *dev) clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E), CCU_ADBASE_DI_MASK); + /* Enable access to DDR from TCU */ + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D), + CCU_ADBASE_DI_MASK); + clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E), + CCU_ADBASE_DI_MASK); + /* this enables nonsecure access to DDR */ /* mpuregion0addr_limit */ FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); @@ -512,9 +307,6 @@ static int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS); - /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ - writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); - /* Initialize memory content if not from warm reset */ if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd); @@ -528,6 +320,9 @@ static int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } + /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + sdram_size_check(&bd); priv->info.base = bd.bi_dram[0].start; @@ -537,80 +332,3 @@ static int sdram_mmr_init_full(struct udevice *dev) return 0; } -static int altera_sdram_ofdata_to_platdata(struct udevice *dev) -{ - struct altera_sdram_platdata *plat = dev->platdata; - fdt_addr_t addr; - - addr = dev_read_addr_index(dev, 0); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - plat->ddr_sch = (void __iomem *)addr; - - addr = dev_read_addr_index(dev, 1); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - plat->iomhc = (void __iomem *)addr; - - addr = dev_read_addr_index(dev, 2); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - plat->hmc = (void __iomem *)addr; - - return 0; -} - -static int altera_sdram_probe(struct udevice *dev) -{ - int ret; - struct altera_sdram_priv *priv = dev_get_priv(dev); - - ret = reset_get_bulk(dev, &priv->resets); - if (ret) { - dev_err(dev, "Can't get reset: %d\n", ret); - return -ENODEV; - } - reset_deassert_bulk(&priv->resets); - - if (sdram_mmr_init_full(dev) != 0) { - puts("SDRAM init failed.\n"); - goto failed; - } - - return 0; - -failed: - reset_release_bulk(&priv->resets); - return -ENODEV; -} - -static int altera_sdram_get_info(struct udevice *dev, - struct ram_info *info) -{ - struct altera_sdram_priv *priv = dev_get_priv(dev); - - info->base = priv->info.base; - info->size = priv->info.size; - - return 0; -} - -static struct ram_ops altera_sdram_ops = { - .get_info = altera_sdram_get_info, -}; - -static const struct udevice_id altera_sdram_ids[] = { - { .compatible = "altr,sdr-ctl-s10" }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(altera_sdram) = { - .name = "altr_sdr_ctl", - .id = UCLASS_RAM, - .of_match = altera_sdram_ids, - .ops = &altera_sdram_ops, - .ofdata_to_platdata = altera_sdram_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata), - .probe = altera_sdram_probe, - .priv_auto_alloc_size = sizeof(struct altera_sdram_priv), -}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h index 096c06cba2..cca4cb35ec 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_s10.h @@ -11,48 +11,6 @@ #define DDR_READ_LATENCY_DELAY 40 #define DDR_ACTIVATE_FAWBANK 0x1 -/* ECC HMC registers */ -#define DDRIOCTRL 0x8 -#define DDRCALSTAT 0xc -#define DRAMADDRWIDTH 0xe0 -#define ECCCTRL1 0x100 -#define ECCCTRL2 0x104 -#define ERRINTEN 0x110 -#define ERRINTENS 0x114 -#define INTMODE 0x11c -#define INTSTAT 0x120 -#define AUTOWB_CORRADDR 0x138 -#define ECC_REG2WRECCDATABUS 0x144 -#define ECC_DIAGON 0x150 -#define ECC_DECSTAT 0x154 -#define HPSINTFCSEL 0x210 -#define RSTHANDSHAKECTRL 0x214 -#define RSTHANDSHAKESTAT 0x218 - -#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 -#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) -#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) -#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) -#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) -#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) -#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) -#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) -#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff -#define DDR_HMC_CORE2SEQ_INT_REQ 0xF -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) -#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f - -#define DDR_HMC_ERRINTEN_INTMASK \ - (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ - DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) - /* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -79,110 +37,6 @@ #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4 -/* HMC MMR IO48 registers */ -#define CTRLCFG0 0x28 -#define CTRLCFG1 0x2c -#define DRAMTIMING0 0x50 -#define CALTIMING0 0x7c -#define CALTIMING1 0x80 -#define CALTIMING2 0x84 -#define CALTIMING3 0x88 -#define CALTIMING4 0x8c -#define CALTIMING9 0xa0 -#define DRAMADDRW 0xa8 -#define DRAMSTS 0xec -#define NIOSRESERVED0 0x110 -#define NIOSRESERVED1 0x114 -#define NIOSRESERVED2 0x118 - -#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) -#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ - (((x) >> 5) & 0x1F) -#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ - (((x) >> 10) & 0xF) -#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ - (((x) >> 14) & 0x3) -#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ - (((x) >> 16) & 0x7) - -#define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) -#define CTRLCFG0_CFG_DIMM_TYPE(x) \ - (((x) >> 4) & 0x7) -#define CTRLCFG0_CFG_AC_POS(x) \ - (((x) >> 7) & 0x3) -#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ - (((x) >> 9) & 0x1F) - -#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) -#define CTRLCFG1_CFG_ADDR_ORDER(x) \ - (((x) >> 5) & 0x3) -#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ - (((x) >> 7) & 0x1) - -#define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) - -#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING0_CFG_ACT_TO_PCH(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING0_CFG_ACT_TO_ACT(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ - (((x) >> 18) & 0x3F) - -#define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING1_CFG_RD_TO_RD_DC(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING1_CFG_RD_TO_RD_DB(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING1_CFG_RD_TO_WR(x) \ - (((x) >> 18) & 0x3F) -#define CALTIMING1_CFG_RD_TO_WR_DC(x) \ - (((x) >> 24) & 0x3F) - -#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING2_CFG_WR_TO_WR(x) \ - (((x) >> 18) & 0x3F) -#define CALTIMING2_CFG_WR_TO_WR_DC(x) \ - (((x) >> 24) & 0x3F) - -#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING3_CFG_WR_TO_RD(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING3_CFG_WR_TO_RD_DC(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING3_CFG_WR_TO_RD_DB(x) \ - (((x) >> 18) & 0x3F) -#define CALTIMING3_CFG_WR_TO_PCH(x) \ - (((x) >> 24) & 0x3F) - -#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING4_CFG_PCH_TO_VALID(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING4_CFG_ARF_TO_VALID(x) \ - (((x) >> 18) & 0xFF) -#define CALTIMING4_CFG_PDN_TO_VALID(x) \ - (((x) >> 26) & 0x3F) - -#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) - -/* Firewall DDR scheduler MPFE */ -#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 -#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) +#include "sdram_soc64.h" #endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c new file mode 100644 index 0000000000..985a108b1c --- /dev/null +++ b/drivers/ddr/altera/sdram_soc64.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> +#include <linux/sizes.h> + +#define PGTABLE_OFF 0x4000 + +u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) +{ + return readl(plat->iomhc + reg); +} + +u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) +{ + return readl(plat->hmc + reg); +} + +u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, + u32 data, u32 reg) +{ + return writel(data, plat->hmc + reg); +} + +u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, + u32 reg) +{ + return writel(data, plat->ddr_sch + reg); +} + +int emif_clear(struct altera_sdram_platdata *plat) +{ + hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); + + return wait_for_bit_le32((const void *)(plat->hmc + + RSTHANDSHAKESTAT), + DDR_HMC_RSTHANDSHAKE_MASK, + false, 1000, false); +} + +int emif_reset(struct altera_sdram_platdata *plat) +{ + u32 c2s, s2c, ret; + + c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; + s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; + + debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, hmc_readl(plat, NIOSRESERVED0), + hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2), + hmc_readl(plat, DRAMSTS)); + + if (s2c && emif_clear(plat)) { + printf("DDR: emif_clear() failed\n"); + return -1; + } + + debug("DDR: Triggerring emif reset\n"); + hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); + + /* if seq2core[3] = 0, we are good */ + ret = wait_for_bit_le32((const void *)(plat->hmc + + RSTHANDSHAKESTAT), + DDR_HMC_SEQ2CORE_INT_RESP_MASK, + false, 1000, false); + if (ret) { + printf("DDR: failed to get ack from EMIF\n"); + return ret; + } + + ret = emif_clear(plat); + if (ret) { + printf("DDR: emif_clear() failed\n"); + return ret; + } + + debug("DDR: %s triggered successly\n", __func__); + return 0; +} + +int poll_hmc_clock_status(void) +{ + return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_HMC_CLK), + SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); +} + +void sdram_clear_mem(phys_addr_t addr, phys_size_t size) +{ + phys_size_t i; + + if (addr % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: address 0x%llx is not cacheline size aligned.\n", + addr); + hang(); + } + + if (size % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: size 0x%llx is not multiple of cacheline size\n", + size); + hang(); + } + + /* Use DC ZVA instruction to clear memory to zeros by a cache line */ + for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("dc zva, %0" + : + : "r"(addr) + : "memory"); + addr += CONFIG_SYS_CACHELINE_SIZE; + } +} + +void sdram_init_ecc_bits(bd_t *bd) +{ + phys_size_t size, size_init; + phys_addr_t start_addr; + int bank = 0; + unsigned int start = get_timer(0); + + icache_enable(); + + start_addr = bd->bi_dram[0].start; + size = bd->bi_dram[0].size; + + /* Initialize small block for page table */ + memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); + gd->arch.tlb_addr = start_addr + PGTABLE_OFF; + gd->arch.tlb_size = PGTABLE_SIZE; + start_addr += PGTABLE_SIZE + PGTABLE_OFF; + size -= (PGTABLE_OFF + PGTABLE_SIZE); + dcache_enable(); + + while (1) { + while (size) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + sdram_clear_mem(start_addr, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + + bank++; + if (bank >= CONFIG_NR_DRAM_BANKS) + break; + + start_addr = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + } + + dcache_disable(); + icache_disable(); + + printf("SDRAM-ECC: Initialized success with %d ms\n", + (unsigned int)get_timer(start)); +} + +void sdram_size_check(bd_t *bd) +{ + phys_size_t total_ram_check = 0; + phys_size_t ram_check = 0; + phys_addr_t start = 0; + int bank; + + /* Sanity check ensure correct SDRAM size specified */ + debug("DDR: Running SDRAM size sanity check\n"); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start = bd->bi_dram[bank].start; + while (ram_check < bd->bi_dram[bank].size) { + ram_check += get_ram_size((void *)(start + ram_check), + (phys_size_t)SZ_1G); + } + total_ram_check += ram_check; + ram_check = 0; + } + + /* If the ram_size is 2GB smaller, we can assume the IO space is + * not mapped in. gd->ram_size is the actual size of the dram + * not the accessible size. + */ + if (total_ram_check != gd->ram_size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) +{ + u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + + phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + + size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + + return size; +} + +static int altera_sdram_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_sdram_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->ddr_sch = (void __iomem *)addr; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->iomhc = (void __iomem *)addr; + + addr = dev_read_addr_index(dev, 2); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->hmc = (void __iomem *)addr; + + return 0; +} + +static int altera_sdram_probe(struct udevice *dev) +{ + int ret; + struct altera_sdram_priv *priv = dev_get_priv(dev); + + ret = reset_get_bulk(dev, &priv->resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&priv->resets); + + if (sdram_mmr_init_full(dev) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + return 0; + +failed: + reset_release_bulk(&priv->resets); + return -ENODEV; +} + +static int altera_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_sdram_ops = { + .get_info = altera_sdram_get_info, +}; + +static const struct udevice_id altera_sdram_ids[] = { + { .compatible = "altr,sdr-ctl-s10" }, + { .compatible = "intel,sdr-ctl-agilex" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_sdram_ids, + .ops = &altera_sdram_ops, + .ofdata_to_platdata = altera_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata), + .probe = altera_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_sdram_priv), +}; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h new file mode 100644 index 0000000000..7b25a80ae2 --- /dev/null +++ b/drivers/ddr/altera/sdram_soc64.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + */ + +#ifndef _SDRAM_SOC64_H_ +#define _SDRAM_SOC64_H_ + +#include <common.h> +#include <linux/sizes.h> + +struct altera_sdram_priv { + struct ram_info info; + struct reset_ctl_bulk resets; +}; + +struct altera_sdram_platdata { + void __iomem *hmc; + void __iomem *ddr_sch; + void __iomem *iomhc; +}; + +/* ECC HMC registers */ +#define DDRIOCTRL 0x8 +#define DDRCALSTAT 0xc +#define DRAMADDRWIDTH 0xe0 +#define ECCCTRL1 0x100 +#define ECCCTRL2 0x104 +#define ERRINTEN 0x110 +#define ERRINTENS 0x114 +#define INTMODE 0x11c +#define INTSTAT 0x120 +#define AUTOWB_CORRADDR 0x138 +#define ECC_REG2WRECCDATABUS 0x144 +#define ECC_DIAGON 0x150 +#define ECC_DECSTAT 0x154 +#define HPSINTFCSEL 0x210 +#define RSTHANDSHAKECTRL 0x214 +#define RSTHANDSHAKESTAT 0x218 + +#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) +#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) +#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) +#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) +#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) +#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) +#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) +#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) +#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) +#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) +#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) +#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) +#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) +#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) +#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_CORE2SEQ_INT_REQ 0xF +#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) +#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f + +#define DDR_HMC_ERRINTEN_INTMASK \ + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) + +/* HMC MMR IO48 registers */ +#define CTRLCFG0 0x28 +#define CTRLCFG1 0x2c +#define CTRLCFG3 0x34 +#define DRAMTIMING0 0x50 +#define CALTIMING0 0x7c +#define CALTIMING1 0x80 +#define CALTIMING2 0x84 +#define CALTIMING3 0x88 +#define CALTIMING4 0x8c +#define CALTIMING9 0xa0 +#define DRAMADDRW 0xa8 +#define DRAMSTS 0xec +#define NIOSRESERVED0 0x110 +#define NIOSRESERVED1 0x114 +#define NIOSRESERVED2 0x118 + +#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ + (((x) >> 0) & 0x1F) +#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ + (((x) >> 5) & 0x1F) +#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ + (((x) >> 10) & 0xF) +#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ + (((x) >> 14) & 0x3) +#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ + (((x) >> 16) & 0x7) + +#define CTRLCFG0_CFG_MEMTYPE(x) \ + (((x) >> 0) & 0xF) +#define CTRLCFG0_CFG_DIMM_TYPE(x) \ + (((x) >> 4) & 0x7) +#define CTRLCFG0_CFG_AC_POS(x) \ + (((x) >> 7) & 0x3) +#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ + (((x) >> 9) & 0x1F) + +#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ + (((x) >> 0) & 0x1F) +#define CTRLCFG1_CFG_ADDR_ORDER(x) \ + (((x) >> 5) & 0x3) +#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ + (((x) >> 7) & 0x1) + +#define DRAMTIMING0_CFG_TCL(x) \ + (((x) >> 0) & 0x7F) + +#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING0_CFG_ACT_TO_PCH(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING0_CFG_ACT_TO_ACT(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ + (((x) >> 18) & 0x3F) + +#define CALTIMING1_CFG_RD_TO_RD(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING1_CFG_RD_TO_RD_DC(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING1_CFG_RD_TO_RD_DB(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING1_CFG_RD_TO_WR(x) \ + (((x) >> 18) & 0x3F) +#define CALTIMING1_CFG_RD_TO_WR_DC(x) \ + (((x) >> 24) & 0x3F) + +#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING2_CFG_WR_TO_WR(x) \ + (((x) >> 18) & 0x3F) +#define CALTIMING2_CFG_WR_TO_WR_DC(x) \ + (((x) >> 24) & 0x3F) + +#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING3_CFG_WR_TO_RD(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING3_CFG_WR_TO_RD_DC(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING3_CFG_WR_TO_RD_DB(x) \ + (((x) >> 18) & 0x3F) +#define CALTIMING3_CFG_WR_TO_PCH(x) \ + (((x) >> 24) & 0x3F) + +#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ + (((x) >> 0) & 0x3F) +#define CALTIMING4_CFG_PCH_TO_VALID(x) \ + (((x) >> 6) & 0x3F) +#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ + (((x) >> 12) & 0x3F) +#define CALTIMING4_CFG_ARF_TO_VALID(x) \ + (((x) >> 18) & 0xFF) +#define CALTIMING4_CFG_PDN_TO_VALID(x) \ + (((x) >> 26) & 0x3F) + +#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ + (((x) >> 0) & 0xFF) + +/* Firewall DDR scheduler MPFE */ +#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 +#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) + +u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, + u32 data, u32 reg); +u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, + u32 reg); +int emif_clear(struct altera_sdram_platdata *plat); +int emif_reset(struct altera_sdram_platdata *plat); +int poll_hmc_clock_status(void); +void sdram_clear_mem(phys_addr_t addr, phys_size_t size); +void sdram_init_ecc_bits(bd_t *bd); +void sdram_size_check(bd_t *bd); +phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat); +int sdram_mmr_init_full(struct udevice *dev); + +#endif /* _SDRAM_SOC64_H_ */ |