diff options
author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2018-05-10 13:28:31 +1200 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2018-05-14 10:01:56 +0200 |
commit | db363dbce705d3092f05a622ddea1d007ececca6 (patch) | |
tree | b0d9f3961c8b1fe3fefe9a355ee45e6169db35a4 /drivers/ddr | |
parent | e6f61622d32327907f824154c7f88ddce3c700cc (diff) |
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr')
-rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.c | 2 | ||||
-rw-r--r-- | drivers/ddr/marvell/a38x/mv_ddr_plat.h | 1 | ||||
-rw-r--r-- | drivers/ddr/marvell/a38x/xor.c | 3 |
3 files changed, 5 insertions, 1 deletions
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index 2070bb38b0..2f318cb9ea 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -995,7 +995,7 @@ static u32 ddr3_get_device_size(u32 cs) } } -static int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size) +int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size) { u32 cs_mem_size; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h index 61f10302fc..9c5fdecd93 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h @@ -232,4 +232,5 @@ u32 mv_ddr_dm_pad_get(void); int mv_ddr_pre_training_fixup(void); int mv_ddr_post_training_fixup(void); int mv_ddr_manual_cal_do(void); +int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size); #endif /* _MV_DDR_PLAT_H */ diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c index 024cecd777..f859596d89 100644 --- a/drivers/ddr/marvell/a38x/xor.c +++ b/drivers/ddr/marvell/a38x/xor.c @@ -347,6 +347,9 @@ void ddr3_new_tip_ecc_scrub(void) for (cs_c = 0; cs_c < max_cs; cs_c++) cs_ena |= 1 << cs_c; + /* assume that all CS have same size */ + ddr3_calc_mem_cs_size(0, &cs_mem_size); + mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); total_mem_size = max_cs * cs_mem_size; mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef); |