diff options
| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2019-05-07 17:42:30 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-05-10 22:48:11 +0200 |
| commit | 1085bb3cbaf8321fdc8d0eaa367192433bd51d44 (patch) | |
| tree | 099e967755262df7e02f0ce5a23172cfb2373f93 /drivers/fpga/socfpga_arria10.c | |
| parent | f61d52926086bf56c870f06ba5e88bdb41ac246e (diff) | |
spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'drivers/fpga/socfpga_arria10.c')
| -rw-r--r-- | drivers/fpga/socfpga_arria10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 9df2c430d7..285280e507 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -69,7 +69,7 @@ static int wait_for_user_mode(void) 1, FPGA_TIMEOUT_MSEC, false); } -static int is_fpgamgr_early_user_mode(void) +int is_fpgamgr_early_user_mode(void) { return (readl(&fpga_manager_base->imgcfg_stat) & ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0; |