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| author | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:27:24 +0530 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-20 23:59:44 +0800 |
| commit | f288d54936d7360e934132a128d7e92d3b1c95a0 (patch) | |
| tree | 45e1bf51b45e76cb67291b25057d41ae920f4188 /drivers/fpga/socfpga_arria10.c | |
| parent | aa30aae8b4e8c871a263ad67c4b4fdca236bf7c1 (diff) | |
ram: rk3399: Configure soc odt support
CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.
These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Diffstat (limited to 'drivers/fpga/socfpga_arria10.c')
0 files changed, 0 insertions, 0 deletions