diff options
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2019-08-05 15:54:59 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-10-08 09:11:14 +0200 |
| commit | 26e054c943a7348904a8b432fc9a85185b0861c7 (patch) | |
| tree | e9fe6b1ff6f4f9e1907df5390b59bf07fe983766 /drivers/fpga/xilinx.c | |
| parent | 13210cd951046e828ecf3463f0087acbfb4f185e (diff) | |
arm64: versal: fpga: Add PL bit stream load support
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/fpga/xilinx.c')
| -rw-r--r-- | drivers/fpga/xilinx.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index f5135504ee..4b0334b6be 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -226,7 +226,10 @@ int xilinx_info(xilinx_desc *desc) case xilinx_zynqmp: printf("ZynqMP PL\n"); break; - /* Add new family types here */ + case xilinx_versal: + printf("Versal PL\n"); + break; + /* Add new family types here */ default: printf ("Unknown family type, %d\n", desc->family); } @@ -257,6 +260,9 @@ int xilinx_info(xilinx_desc *desc) case csu_dma: printf("csu_dma configuration interface (ZynqMP)\n"); break; + case cfi: + printf("CFI configuration interface (Versal)\n"); + break; /* Add new interface types here */ default: printf ("Unsupported interface type, %d\n", desc->iface); |