diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-06-14 17:43:24 -0700 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-08-12 08:52:01 +0200 |
| commit | 5f93227ce02d9cafa11704c807a80dcbde129f8c (patch) | |
| tree | 16d3a8a64791cac1a2047f16f65666c6e4ca28d7 /drivers/fpga/zynqpl.c | |
| parent | fd2b10b6d6a0d5e94d6b34faa634e9722a5465a8 (diff) | |
fpga: zynqpl: Clear loopback mode during device init
Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.
In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/fpga/zynqpl.c')
| -rw-r--r-- | drivers/fpga/zynqpl.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index aa49e82483..14363c9a5b 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -23,6 +23,7 @@ #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 +#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 @@ -200,6 +201,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) swap = SWAP_DONE; } + /* Clear loopback bit */ + clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); + if (!partialbit) { zynq_slcr_devcfg_disable(); |