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authorGrygorii Strashko <grygorii.strashko@ti.com>2019-11-18 23:04:43 +0200
committerJoe Hershberger <joe.hershberger@ni.com>2019-12-09 09:47:42 -0600
commitb3b9b128d5432f7b17ed4afeffa1dad04eefec0a (patch)
tree3315b9fdca13228a9739ff45457837e33bd08003 /drivers/fpga
parentfb6038390ebe8717a66dd3a4e37bffb96e50c07a (diff)
net: phy: dp83867: Add ability to disable output clock
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable output clock") of mainline linux kernel. Generally, the output clock pin is only used for testing and only serves as a source of RF noise after this. It could be used to daisy-chain PHYs, but this is uncommon. Since the PHY can disable the output, make doing so an option. I do this by adding another enumeration to the allowed values of ti,clk-output-sel. The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might expect: to select the REF_CLK as the output. Rather it meant "keep clock output setting as is", which, depending on PHY strapping, might not be outputting REF_CLK. Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output. Omitting the property will leave the setting as is (which was the previous behavior in this case). Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK. Change this so they generate an error. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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