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authorJagan Teki <jagan@amarulasolutions.com>2019-07-16 17:27:23 +0530
committerKever Yang <kever.yang@rock-chips.com>2019-07-20 23:59:44 +0800
commitaa30aae8b4e8c871a263ad67c4b4fdca236bf7c1 (patch)
treed4e52f1aa4edc2b4566e4acf488d81883df184a6 /drivers/hwspinlock
parent2fb2de33b2d89442d08a7d69f6afb9c7e46aa992 (diff)
ram: rk3399: Add tsel control clock drive
tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/hwspinlock')
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