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authorMarek Vasut <marex@denx.de>2012-11-30 18:17:06 +0000
committerTom Rini <trini@ti.com>2012-12-11 13:17:30 -0700
commit1e2fc0d19bac9bf4f62d259169e902e700a18bad (patch)
tree31cc4f38e278b1ceeb688efed5418aa8ab33c203 /drivers/i2c
parentaff36ea92ec0700cd9241bf01e72956a3ab9600e (diff)
mxs: i2c: Restore speed setting after block reset
The I2C block reset configures the I2C bus speed to strange value. Read the I2C speed from the block before reseting the block and restore it afterwards, so the I2C operates correctly. This issue can be replicated by doing unsuccessful I2C transfer, after such transfer finishes, the I2C block clock speed is misconfigured. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/mxs_i2c.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 006fb919f4..73a6659dd4 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -40,6 +40,7 @@ void mxs_i2c_reset(void)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
int ret;
+ int speed = i2c_get_bus_speed();
ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
if (ret) {
@@ -53,6 +54,8 @@ void mxs_i2c_reset(void)
&i2c_regs->hw_i2c_ctrl1_clr);
writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
+
+ i2c_set_bus_speed(speed);
}
void mxs_i2c_setup_read(uint8_t chip, int len)